DFT Lead Engineer
About The Position
Broadcom's ASIC Product Division is seeking a Principal DFT Engineer for its San Jose, California, Development Center. The successful candidate will lead DFT programs from chip-level DFT specification through implementation and verification, culminating in product release to production. The role covers SoC DFT architecture, test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. It also includes working with Physical Design and STA teams on DFT-mode timing closure and may involve direct interaction with external customers. The engineer will define and implement DFT solutions, generate and debug test vectors, support silicon bring-up and failure analysis, and automate DFT and test-vector generation flows. The position requires coding in TCL, PERL, RUBY, PYTHON, C++ or similar languages and close collaboration with teams and stakeholders across disciplines and locations.
Requirements
- Bachelor's degree in Electrical, Electronic, or Computer Engineering and 12 or more years of relevant industry experience, or a Master's degree in one of these fields and 10 or more years of relevant industry experience.
- Strong DFT background, such as IO and Analog DFT, ATPG, Scan, or BIST.
- Scan insertion and scan compression experience, including tools such as DFT Compiler or Mentor TestKompress.
- Proficiency in ATPG vector generation, simulation, and debugging, using tools such as TetraMax or Fastscan.
- Experience in Verilog coding, testbench generation, and simulation.
- Memory BIST insertion and verification experience with embedded SRAM, CAM, eDRAM, or ROM.
- Boundary-scan verification and test-vector generation experience.
- Good knowledge of IEEE 1149.1 and IEEE 1149.6.
- Basic knowledge of test STA and constraints.
- Strong background in IEEE 1687, IJTAG, ICL, and PDL.
- Ability to work in a multidisciplinary, cross-department environment.
- Solid knowledge of analog and digital circuit design and device-physics fundamentals.
- Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
- Excellent problem-solving, debugging, root-cause analysis, and communication skills.
- Ability to code using TCL, PERL, RUBY, PYTHON, C++ or similar.
Nice To Haves
- Experience working on ATE.
- Experience with SerDes, DDR, PCIE, ENET, or CXL IOBIST verification and silicon debug.
- Experience working on Tessent SSN; highly desired.
Responsibilities
- Understand Broadcom and customer DFT feature requirements and DPPM goals, and define appropriate DFT specifications for ASICs.
- Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integration.
- Work with STA and DI engineers to achieve design closure for test.
- Generate, verify, and debug test vectors before tape release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement.
- Interface with customers and with physical design and test engineering/manufacturing teams located globally.
- Work with I/P DFT engineers and other stakeholders.
- Debug customer-returned parts on ATE.
- Develop newer DFT solutions for testability problems in 7nm and beyond.
- Automate DFT and test-vector generation flows.
Benefits
- Discretionary annual bonus.
- Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays.
- Paid sick leave and vacation time.
- Paid Family Leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
