DFT Lead Engineer

Broadcom•Austin, TX

3d•$143,800 - $230,000•Onsite

About The Position

Broadcom's ASIC Product Division is seeking a DFT engineer for its Austin, Texas Development Center. The role leads DFT programs from chip-level specification through implementation and verification, culminating in product release to production. Work spans SoC DFT architecture, test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. The position works with Physical Design and STA teams on DFT-mode timing closure and may involve direct interaction with external customers. The engineer will define and implement DFT for ASIC designs, generate and debug test vectors before tape release, validate vectors on ATE during silicon bring-up, and support failure analysis and yield improvement. The role also includes cross-functional and customer collaboration, debugging returned parts on ATE, innovating DFT solutions for 7nm and beyond, and automating DFT and test-vector-generation flows. Programming skills in TCL, PERL, RUBY, PYTHON, C++ or similar are expected.

Requirements

Bachelor's degree in Electrical, Electronic, or Computer Engineering and 12+ years of relevant industry experience, or a master's degree in one of those fields and 10+ years of relevant industry experience.
Strong DFT background, such as IO and Analog DFT, ATPG, Scan, or BIST.
Scan insertion and scan compression experience, such as with DFT Compiler or Mentor TestKompress.
Experience with ATPG vector generation, simulation, and debugging, using tools such as TetraMax or Fastscan.
Experience in Verilog coding, testbench generation, and simulation.
Memory BIST insertion and verification experience with embedded SRAM, CAM, eDRAM, or ROM.
Boundary-scan verification and test-vector-generation experience, with knowledge of IEEE 1149.1 and IEEE 1149.6.
Basic knowledge of Test-STA and constraints.
Strong background in IEEE 1687, IJTAG, ICL, and PDL.
Ability to work in a multidisciplinary, cross-department environment.
Knowledge of analog and digital circuit design and device physics fundamentals.
Understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
Excellent problem-solving, debugging, root-cause-analysis, and communication skills.
Ability to code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Nice To Haves

Experience working on ATE.
Experience with SerDes, DDR, PCIE, ENET, or CXL IOBIST verification and silicon debug.
Experience working on Tessent SSN is highly desired.

Responsibilities

Understand Broadcom and customer DFT feature requirements and DPPM goals, and define appropriate ASIC DFT specifications.
Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integration.
Work with STA and DI engineers to achieve design closure for test.
Generate, verify, and debug test vectors before tape release.
Validate and debug test vectors on ATE during silicon bring-up.
Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
Interface with customers and physical design, test engineering, and manufacturing teams located globally.
Work closely with I/P DFT engineers and other stakeholders.
Debug customer-returned parts on ATE.
Innovate DFT solutions to address testability problems in 7nm and beyond.
Automate DFT and test-vector-generation flows.

Benefits

Discretionary annual bonus.
Competitive new-hire equity grant and annual equity awards, subject to plan documents and award agreements.
Medical insurance.
Dental insurance.
Vision insurance.
401(k) participation with company matching.
Employee Stock Purchase Program (ESPP).
Employee Assistance Program (EAP).
Company-paid holidays.
Paid sick leave and vacation time.
Paid Family Leave and other leaves of absence in accordance with applicable laws.