Senior DFT Engineer

NVIDIA•Santa Clara, CA

9d•$168,000 - $310,500•Hybrid

About The Position

NVIDIA’s Design-for-Test Engineering team develops DFT architecture, verification, and post-silicon validation solutions for complex semiconductor chips. The Senior DFT Engineer will implement test access mechanisms, IO BIST, memory BIST, and scan compression, and help develop and deploy DFT methodologies for next-generation products. The role will define, prototype, and deploy DFX architectures and methodologies across NVIDIA products. Areas include high-speed test access, in-system testing, ISO 26262 functional-safety diagnostics for in-field testing, silicon debug and bring-up, productization, and silicon life-cycle management. The engineer will craft DFX architectures and methodologies supporting system-level safety diagnostics, in-field test quality, defect screening and diagnosis, and silicon life-cycle management for automotive, industrial, and robotics safety platforms. The position collaborates with system and chip architecture, ASIC design, verification, CAD, VLSI, software development, and Operations teams to productize new methodologies. It also contributes workflows and tools for NVIDIA processors and mentors junior engineers on test design and cost-quality trade-offs.

Requirements

BSEE or equivalent experience with 8 or more years of experience, MSEE with 5 or more years, or PhD with 3 or more years in DFT or related domains.
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
Excellent analytical skills for verification and validation of test patterns and logic on complex, multi-million-gate designs using vendor tools.
Exposure to cross-functional areas including RTL and clock design, STA, place-and-route, and power to assess design trade-offs.
Experience with silicon debug and bring-up on ATE, including understanding pattern formats, failure processing, and test program development.
Strong written and oral communication skills and curiosity to work on challenging problems.

Nice To Haves

Strong programming and scripting skills in Perl, Python, or Tcl.

Responsibilities

Implement test access mechanisms, IO BIST, memory BIST, and scan compression in collaboration with cross-functional teams.
Develop and deploy DFT methodologies for next-generation products.
Define, prototype, and deploy DFX architectures and methodologies across NVIDIA products.
Develop high-speed test access and in-system-test architectures, functional-safety diagnostics for in-field testing, and approaches for silicon debug, bring-up, productization, and silicon life-cycle management.
Craft DFX architectures and methodologies to meet system-level safety diagnostic and in-field test quality goals and enable defect screening, diagnosis, and silicon life-cycle management for automotive, industrial, and robotics safety platforms.
Collaborate with system architecture, chip architecture, ASIC design, verification, CAD, VLSI, software development, and Operations teams to productize new methodologies.
Help deliver efficient workflows and tools to productize features on NVIDIA processors.
Mentor junior engineers on test designs and cost-quality trade-offs.