Senior DFT Design Engineer

Intel•Folsom, CA

3d•Hybrid

About The Position

Intel is seeking Senior DFT Design Engineers for its GPU Hardware IP (GHI) DFT group, which designs and validates next-generation graphics engines. The role focuses on graphics and visual computing, with work spanning design, RTL/GLS validation, automation, and timing analysis for Scan/ATPG. Engineers may also contribute to trace and pattern generation, post-silicon enablement, debug support, and ATPG content analysis. The position includes developing logic design, RTL, and simulations for graphics IP, including graphics, compute, display, and media components, as well as supporting GPU IP integration into full-chip designs. The engineer participates in block architecture and microarchitecture definition, applies design strategies and tools to meet power, performance, area, timing, and physical implementation goals, and helps ensure design correctness through verification planning, unit-level verification, and resolution of failing RTL tests. The role also supports SoC customers with high-quality GPU block integration.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field and 4 or more years of industry experience; or a master's degree in one of these fields and 3 or more years of industry experience; or a Ph.D. in one of these fields and 1 or more years of industry experience.
Experience with Scan, ATPG, or other DFT features.
Experience in SoC or IP DFT design, integration, or verification.
Experience with EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS, and/or other simulation or debug tools.

Nice To Haves

Silicon enabling, debug, or test pattern development experience.
Design automation skills and proficiency in programming or scripting languages.
Experience with structural design flows, including timing, routing, placement, or clocking analysis.
Experience with high-volume manufacturing requirements and test flows.
Experience with 3D, media, and display graphics pipelines.
SoC architecture experience.

Responsibilities

Perform design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG.
Contribute to trace and pattern generation, post-silicon enablement, debug support, and/or ATPG content analysis.
Develop logic design, RTL coding, and simulation for graphics IP, including graphics, compute, display, and media.
Participate in architecture and microarchitecture feature definition for the block being designed.
Write RTL and optimize logic to meet power, performance, area, and timing goals and design integrity requirements for physical implementation.
Review verification plans and implementations to ensure design features are verified across verification hierarchies.
Drive unit-level verification and resolve failing RTL tests by implementing corrective measures.
Support SoC customers to ensure high-quality integration of the GPU block.