Senior DFT Design Engineer

Intel Corporation•Santa Clara, CA

4d•$141,910 - $172,860•Hybrid

About The Position

Intel is seeking Senior DFT Design Engineers for its GPU Hardware IP (GHI) DFT group, contributing to graphics and visual computing technology. The role includes design, RTL/GLS validation, automation, and timing analysis for Scan/ATPG, as well as potential work on trace and pattern generation, post-silicon enablement, debug support, and ATPG content analysis. The engineer develops logic design, RTL code, and simulations for graphics IP, including graphics, compute, display, and media. Responsibilities also include participating in block architecture and microarchitecture definition; applying tools and methods to meet power, performance, area, timing, and physical implementation goals; reviewing verification plans and implementation; driving unit-level verification; resolving RTL test failures; and supporting SoC customers with high-quality GPU block integration. The GHI team, part of Intel's Data Center Group, designs and validates next-generation graphics engines and works on high-performance visual computing solutions. This position is hybrid, with the option to split time between an assigned Intel site and off-site work. Primary location is Folsom, California, with additional locations in Phoenix, Arizona; Santa Clara, California; and Hillsboro, Oregon.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field and 4 or more years of industry experience; or a master's degree in one of these fields and 3 or more years of industry experience; or a Ph.D. in one of these fields and 1 or more years of industry experience.
Experience with Scan, ATPG, or other DFT features.
Experience with SoC or IP DFT design, integration, or verification.
Experience with EDA tools such as Siemens Tessent or other ATPG tools, and Synopsis VCS and/or other simulation or debug tools.

Nice To Haves

Silicon enablement, debug, or test pattern development experience.
Design automation skills and proficiency in programming or scripting languages.
Experience with structural design flows, including timing, routing, placement, or clocking analysis.
Experience with high-volume manufacturing requirements and test flows.
Experience with 3D, media, and display graphics pipelines.
SoC architecture experience.

Responsibilities

Design, validate, automate, and/or perform timing analysis for Scan/ATPG.
Contribute to or participate in trace and pattern generation, post-silicon enablement, debug support, and analysis of ATPG content.
Develop logic design, RTL code, and simulations for graphics IP, including graphics, compute, display, and media.
Participate in defining architecture and microarchitecture features for the block being designed.
Apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals, while supporting design integrity for physical implementation.
Review verification plans and implementation to ensure design features are correctly verified across verification hierarchies.
Drive unit-level verification and resolve and implement corrective measures for failing RTL tests.
Support SoC customers to ensure high-quality GPU block integration.