Senior Principal Engineer-DFT
About The Position
Marvell is seeking a senior technical leader to serve as a DFT Lead for next-generation Optical DSP (ODSP) programs. The ODSP team, part of the Connectivity Business Unit, develops advanced ASICs for hyperscale data centers, enterprise, and AI infrastructure, including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers. Its products support high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. The team develops chips using TSMC advanced process nodes and operates across Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina. The role is responsible for architecting, leading, and implementing DFT and test methodology for a complex mixed-signal SoC across multiple generations. The work spans DFT architecture definition, implementation of DFT/DFX features, validation, IP-DFT, STA, pattern generation, and post-silicon bring-up and debug for designs and IP in the custom and compute space. The position also leads, mentors, and guides a team of DFT engineers, and defines and enhances DFT methodologies and tools, including benchmarking and enabling new methodologies.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 15+ years of related professional experience; alternatively, a Master’s degree and/or PhD in these fields with 13+ years of experience.
- Hands-on experience across DFT execution stages, including SCAN, MBIST, validation, STA, IP-DFX, and post-silicon bring-up and debug.
- Thorough knowledge of DFT/test architecture solutions and participation in DFT architecture definition for at least a couple of designs.
- Strong fundamentals in digital circuit design and logic design.
- Understanding of DFT flows and methodologies.
- Experience with Cadence, Mentor, or Synopsys tool sets, including Genus, Modus, NCSim, DC, Tessent, Spyglass, or Tmax.
Nice To Haves
- Prior experience in ASIC design.
- Scripting skills using Python, PERL, Tcl, and C-Shell.
Responsibilities
- Architect, lead, and implement DFT and test methodology for a complex mixed-signal SoC across multiple generations.
- Define DFT architecture and implement DFT/DFX features.
- Perform validation, IP-DFT, STA, pattern generation, and post-silicon bring-up and debug for designs and IP.
- Mentor, guide, and lead a team of DFT engineers, enabling the team to scale across multiple designs.
- Define and enhance DFT methodologies and tools, benchmark them, and enable new DFT/test methodologies.
Benefits
- Eligible to participate in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Employee stock purchase plan with a 2-year look back.
- Family support programs.
- Mental health resources.
- Recognition and service awards.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
