Senior Principal Engineer-DFT
About The Position
Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced ASICs for hyperscale data center, enterprise, and AI infrastructure markets. Its products include multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers supporting high-bandwidth data transmission across optical fiber networks and electrical interconnects. The team develops chips using advanced TSMC process nodes and operates as a global, multi-site engineering organization. The Senior Principal Engineer-DFT will serve as a technical DFT lead for next-generation ODSP programs. The role architects, leads, and implements DFT and test methodology for complex mixed-signal SoCs across multiple generations. It covers DFT/test architecture, DFT/DFX implementation, validation, IP-DFT, STA, pattern generation, and post-silicon bring-up and debug. The role also mentors and guides a team of DFT engineers, helps scale DFT across multiple designs, and defines and improves DFT methodologies and tools, including benchmarking and enabling new approaches.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 15+ years of related professional experience; alternatively, a Master’s degree and/or PhD in these fields with 13+ years of experience.
- Hands-on experience in various stages of DFT execution, including SCAN, MBIST, validation, STA, IP-DFX, and post-silicon bring-up/debug.
- Thorough knowledge of DFT/test architecture solutions and involvement in DFT architecture definition for at least a couple of designs.
- Strong fundamentals in digital circuit design and logic design.
- Understanding of DFT flows and methodologies.
- Experience with Cadence, Mentor, or Synopsys tool sets, including tools such as Genus, Modus, NCSim, DC, Tessent, Spyglass, or Tmax.
Nice To Haves
- Prior experience in ASIC design.
- Scripting skills using Python, Perl, Tcl, and C-Shell.
Responsibilities
- Architect, lead, and implement DFT and test methodology for complex mixed-signal SoCs across multiple generations.
- Define DFT/test architecture and implement DFT/DFX features.
- Execute validation, IP-DFT, STA, pattern generation, and post-silicon bring-up and debug for designs and IPs in the Custom/Compute space.
- Mentor, guide, and drive a team of DFT engineers to support scaling across multiple designs.
- Define and enhance DFT methodologies and tools, benchmark them, and enable new methodologies in DFT/test.
Benefits
- Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Employee stock purchase plan with a 2-year look back.
- Family support programs.
- Mental health resources.
- Recognition and service awards.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
