Senior Cache Coherency Architect

NVIDIA•Santa Clara, CA

6d•$152,000 - $287,500

About The Position

NVIDIA is seeking an experienced Senior Cache Coherency Architect to help develop scalable, low-latency, high-bandwidth coherent interconnect systems that power products including Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin. The role contributes to the architecture of cache-coherent interconnects and cache subsystems, including architecture definition, modeling, and implementation. The architect works with CPU, GPU, memory subsystem, and SoC architects to define coherency solutions for SoC designs, and partners with IP creation and verification teams throughout the project lifecycle. The work can impact product lines spanning consumer graphics, automotive, and AI platforms. The position also supports silicon bring-up and post-silicon debug as needed.

Requirements

Master’s degree in electrical engineering, computer engineering, computer science, or equivalent experience.
At least 5 years of experience in processor design or other high-performance semiconductor designs.
Deep understanding of cache coherency and hands-on experience with industry-standard protocols such as AXI, ACE, or CHI.
Experience authoring specifications and designing cache-coherent interconnects.
Strong understanding of system and memory subsystem architecture, focused on cache-coherent interconnect.
Experience developing coherent IP models, such as VIPs or BFMs, for simulation and emulation.
Proficiency in C, C++, Python, and Verilog.

Responsibilities

Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
Contribute to interconnect IP block specifications, development, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
Collaborate with architects to ensure the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
Develop and maintain functional and performance models for the NoC fabric and IP units to support analysis and validation.
Work with cross-functional design and verification teams, including simulation, emulation, and formal teams, to ensure implementations align with architectural specifications.
Support silicon bring-up and post-silicon debug as needed.