Senior Silicon Architect – Cache Coherent Interconnects
About The Position
As a member of NVIDIA’s CPU Cache Coherent Interconnects Design Team, the Senior Silicon Architect owns the silicon architecture and construction plan for next-generation CPU processors. The work focuses on dielet partitioning, packaging and die-stacking exploration, floorplanning, and die-to-die interface planning. The role supports product lines spanning consumer graphics, self-driving cars, and artificial intelligence, working with a global team to develop future computing platforms. The position involves exploring 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions, including placement of IO and compute components such as CPU cores, caches, and NOC across dielets. The architect develops early floorplans and plans die-to-die and off-chip IO, including UCIe, DRAM, and PCIe. They collaborate with architecture, logic design, physical design, and packaging teams to achieve area, performance, power, and thermal goals.
Requirements
- Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
- At least 8 years of experience in processor or other related high-performance semiconductor designs.
- Deep understanding of digital design, CPU system architecture, and ASIC floor-planning, including wire densities on-die and across 3D-connected dies.
- Strong communication and interpersonal skills.
- Ability to work in a dynamic, global team.
Nice To Haves
- A strong background in cache coherency or high-speed interconnects and industry-standard coherency, IO, or memory protocols.
- Knowledge of advanced packaging, including TSMC InFO and CoWoS, Intel EMIB, through-silicon via configurations, and backside power delivery.
- Knowledge of dielet, interposer, and substrate connectivity.
Responsibilities
- Own the silicon architecture and construction plan for next-generation CPU processors.
- Explore 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions.
- Plan the placement of IO and compute components, including CPU cores, caches, and NOC, across dielets.
- Develop early floorplans.
- Plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe.
- Work with architecture, logic design, physical design, and packaging teams to achieve area, performance, power, and thermal goals.
Benefits
- Equity
- Benefits (not specified)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
