Silicon Architect, Subsystem Architecture

Meta•Redmond, WA

2d•$114,000 - $172,000

About The Position

Reality Labs develops advanced AR- and AI-enabled wearables, whose compute performance and power-efficiency requirements call for custom silicon. The Reality Labs Silicon team works across AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors, addressing the technology stack from transistors through architecture, firmware, and algorithms. As a Memory Architect on the Subsystem Architecture team, you will work with senior memory architects to analyze and define on-chip memory for accelerator subsystems and IPs in wearable chips. This includes caches, scratchpads, and SRAM selection, balancing power, performance, and area (PPA) within tight wearable-device budgets. The role supports memory analysis and architecture decisions across multiple programs, with the opportunity to eventually own end-to-end analysis and next-generation memory system architecture for one or more subsystems.

Requirements

Currently has or is pursuing a bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; the degree must be completed before joining Meta.
At least 2 years of experience in silicon architecture, memory design, or related silicon engineering disciplines.
Experience through industry, internships, or graduate research in at least one of memory hierarchy and cache analysis or SRAM circuit design.
Understanding of how memory technologies, architectures, and microarchitectures—such as SRAM bitcell, Vmin, leakage, and banking—affect the power, performance, and area of memory-intensive systems.
Experience building analytical, functional, and cycle-accurate models to evaluate memory trade-offs.

Nice To Haves

Publications at venues such as ISCA, MICRO, HPCA, ISSCC, or VLSI Symposium.
Experience with SPICE, memory compilers, or low-voltage SRAM.
Experience sizing caches, scratchpads, or DSP memories for accelerator workloads.
Research or industry experience with emerging memory technologies.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with research in memory systems or memory circuits.
Experience in both memory hierarchy and cache analysis and SRAM circuit design.

Responsibilities

Analyze memory requirements for workloads across accelerator subsystems, including caches, scratchpads, and DSP local memories.
Evaluate SRAM options, including compiled or custom SRAM, bitcells, banking, low-voltage operation, and retention modes, and recommend the best fit for each memory.
Build memory models and power, performance, and area comparisons to inform architecture decisions.
Support studies of memory hierarchy trade-offs, such as cache sizing and on-chip versus off-chip memory, and eventually own end-to-end analysis and next-generation memory system architecture for one or more subsystems.
Track emerging memory technologies, including MRAM, RRAM, eDRAM, 3D-stacked memory, and compute-in-memory, and assess their fit for wearable subsystems.
Correlate memory estimates with pre-silicon and silicon data and inform improvements to modeling methodologies.
Collaborate with senior memory architects, IP and DSP architects, memory and circuit design teams, and software and firmware teams across multiple programs.