Sr. Staff PCIE Subsystem Architect

Qualcomm • San Diego, CA

4d • $216,600 - $325,000

About The Position

Qualcomm is seeking an experienced PCIe Subsystem Architect to define and deliver high-performance I/O architectures for next-generation datacenter AI products. The role focuses on PCIe and CXL, defining subsystem architecture and driving requirements from accelerator cards and servers through full-rack scale-up and scale-out deployments.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field and 8+ years of Systems Engineering or related work experience; OR a master's degree in one of these fields and 7+ years of such experience; OR a PhD in one of these fields and 6+ years of such experience.
• 2+ years of experience in one or more system architecture technology areas and products, such as Power System, Shared Resource Management, Limits/Thermal Management, or Hardware Islands.
• Deep expertise across PCIe and CXL.
• Knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
• Understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
• Experience with PCIe error containment and recovery mechanisms, including AER, DPC, CRS, FLR, and reset separation.
• Experience with I/O virtualization and isolation technologies, including SR-IOV, SIOV, and PF/VF isolation, and related software-visible requirements.
• Understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Knowledge of PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
• Ability to work effectively in a high-caliber, international, multi-site engineering team.

Nice To Haves

• Understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
• Familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
• Understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
• Understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
• Understanding of high-speed SerDes and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
• Knowledge of server SoC architectures, particularly security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
• Ability to engage with customers, product management, systems teams, and cross-functional architecture stakeholders to gather requirements and drive technical alignment.
• Excellent written and verbal communication skills, including the ability to create architecture specifications, requirement documents, and executive-level technical summaries.

Responsibilities

• Define subsystem architecture for high-performance I/O in next-generation datacenter AI products.
• Drive requirements from accelerator-card and server levels through full-rack scale-up and scale-out deployments.
• Apply knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Address PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
• Address PCIe Gen6 and Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
• Address PCIe error containment and recovery mechanisms, including AER, DPC, CRS, FLR, and reset separation.
• Address I/O virtualization and isolation technologies, including SR-IOV, SIOV, and PF/VF isolation, and their software-visible requirements.
• Account for RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Consider PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment.
• Work effectively with an international, multi-site engineering team.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior