Senior Logic Design Engineer, Cache Coherent Interconnects

NVIDIA•Santa Clara, CA

7d•$136,000 - $264,500•Hybrid

About The Position

As a member of NVIDIA’s CPU Logic Design Team, the Senior Logic Design Engineer designs CPU on-chip and off-chip interconnect networks, multiprocessor coherency, and last-level and system caches. The work includes micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, and supporting verification and implementation. The engineer owns a specific chip unit and is responsible for crafting and delivering it on time. The role involves writing readable, high-performance, low-power RTL, documenting the design, collaborating with verification, working with implementation teams to meet timing, area, performance, and power goals, and assisting with timing closure of super units. The position is part of a global team working on products across consumer graphics, self-driving cars, and artificial intelligence.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
At least 5 years of experience in processor or other related high-performance semiconductor designs.
Verilog expertise.
Deep understanding of ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
Strong communication and interpersonal skills for working in a dynamic, global team.

Nice To Haves

A successful track record of mentoring junior engineers and interns.
A strong background in computer architecture, cache coherency, or high-speed interconnects.

Responsibilities

Own a specific chip unit and ensure its timely delivery.
Design CPU on-chip and off-chip interconnect networks, multiprocessor coherency, and last-level and system caches.
Define micro-architecture and write readable, high-performance, low-power RTL.
Perform synthesis, logic debug, and timing closure.
Create design documentation.
Collaborate with the verification team to verify unit correctness.
Work with implementation teams to achieve timing, area, performance, and power goals.
Assist with timing closure of super units.