Senior Logic Design Engineer
About The Position
Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) organization develops the infrastructure and foundational technologies that power Microsoft’s online services and Azure platform. Within SCHIE, Compute Silicon & Manufacturing Engineering (CSME) designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. The Silicon Logic Design team supports cloud hardware manufacturing by improving planning, quality, delivery, scale, and sustainability. The Senior Logic Design Engineer will design RTL for a high-performance PCIe subsystem supporting Azure Cobalt. The role involves building a subsystem from multiple IP blocks, coordinating with architecture and IP providers to satisfy SoC requirements, refining implementations for area, power, and performance, and completing design quality checks. The engineer will work with cross-functional teams to deliver high-quality functional blocks on schedule.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Ability to provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.
Nice To Haves
- Experience with high-speed PCIe designs and protocols.
- Experience with industry-standard interface protocols such as AXI and APB.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of computer architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl, or similar languages.
- Experience with EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, or Genus.
- Proficiency with UPF and low-power intent.
- Proficiency in clock-crossing techniques.
- Knowledge of Static Timing Analysis and timing signoff fundamentals.
- Applied understanding of low-power design principles.
- Understanding of design-closure challenges involving power and clock-domain crossings.
- Experience writing timing constraints, exceptions, and clock constraints, with understanding of SDC commands and Tcl constraints.
- Organized and detail-oriented.
- Good verbal and written communication skills.
Responsibilities
- Build a PCIe subsystem composed of multiple IP.
- Collaborate with architecture and IP providers to ensure the subsystem meets SoC requirements.
- Develop micro-architectural knowledge of assigned blocks and other blocks in the SoC.
- Assess and refine implementations for area, power, and performance.
- Perform design quality checks, including synthesis, lint, CDC, RDC, low-power intent, and logic equivalence.
- Understand dataflow and clocking requirements and develop solutions for timing-critical paths.
- Automate tasks using scripting.
- Deliver high-quality functional blocks on schedule and with professional integrity.
- Collaborate respectfully with cross-functional team members to establish synergies.
- Challenge the status quo with a growth mindset.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
