Senior Logic Design Engineer
About The Position
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. The Silicon Logic Design team supports hardware manufacturing quality, delivery, scale, planning, and sustainability. The Senior Logic Design Engineer will design RTL for a high-performance PCIe subsystem supporting Azure Cobalt. The role involves building a subsystem from multiple IPs and working with architecture and IP providers to meet SoC requirements. The engineer will refine implementations for area, power, and performance; perform design quality checks; and address dataflow, clocking, and timing-critical-path requirements. The role also involves scripting to automate work and collaborating across teams to deliver high-quality functional blocks on schedule.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Ability to satisfy export-control eligibility verification requirements, including providing proof of citizenship, U.S. residency, or other protected status; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.
Nice To Haves
- Experience with high-speed PCIe designs and protocols.
- Experience with industry-standard interface protocols such as AXI and APB.
- Experience with ARM Fabric IPs.
- Experience with IP-XACT.
- Understanding of computer architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl, or similar languages.
- Experience with EDA tools such as VCS, VCLP, SpyGlass Lint, Questa CDC, Fusion Compiler, Design Compiler, or Genus.
- Proficiency with UPF and low-power intent.
- Proficiency in clock-crossing techniques.
- Knowledge of static timing analysis and timing signoff fundamentals.
- Applied understanding of low-power design principles.
- Understanding of design-closure challenges involving power and clock-domain crossings.
- Experience writing timing constraints, exceptions, and clock constraints, with understanding of SDC commands and Tcl constraints.
- Organized and detail-oriented.
- Good verbal and written communication skills.
Responsibilities
- Build a PCIe subsystem composed of multiple IPs.
- Collaborate with architecture and IP providers to ensure the subsystem meets SoC requirements.
- Develop micro-architectural knowledge of assigned blocks and other blocks in the SoC.
- Assess and refine implementations for area, power, and performance.
- Perform design quality checks, including synthesis, lint, CDC, RDC, low-power intent, and logic equivalence.
- Understand dataflow and clocking requirements and drive solutions for timing-critical paths.
- Automate tasks using scripting for efficiency.
- Deliver high-quality functional blocks on schedule and with professional integrity.
- Collaborate respectfully with cross-functional team members to establish synergies.
- Challenge the status quo with a growth mindset.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
