Senior Silicon Architect – Cache Coherent Interconnects

NVIDIA • Austin, TX

7d

About The Position

As a member of NVIDIA’s CPU Cache Coherent Interconnects Design Team, the Senior Silicon Architect will own the silicon architecture and construction plan for next-generation CPU processors. The work focuses on dielet partitioning, packaging and die-stacking exploration, floorplanning, and die-to-die interface planning. The role covers 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions, including placement of IO and compute components such as CPU cores, caches, and the network-on-chip (NOC). The architect will develop early floorplans and plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe, collaborating with architecture, logic design, physical design, and packaging teams to meet area, performance, power, and thermal goals. The position supports product areas including consumer graphics, self-driving cars, and artificial intelligence. Applicants are eligible for equity and benefits. This posting is for an existing vacancy, and applications will be accepted at least until November 3, 2026.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
• At least 8 years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture, and ASIC floor-planning, including wire densities on-die and across 3D-connected dies.
• Strong communication and interpersonal skills.
• Ability to work in a dynamic, global team.

Nice To Haves

• Background in cache coherency or high-speed interconnects and industry-standard coherency, IO, or memory protocols.
• Knowledge of advanced packaging, including TSMC InFO and CoWoS and Intel EMIB; through-silicon via configurations; backside power delivery; and dielet, interposer, and substrate connectivity.

Responsibilities

• Own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions, including placement of IO and compute components across dielets.
• Develop early floorplans and plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe.
• Collaborate with architecture, logic design, physical design, and packaging teams to achieve area, performance, power, and thermal goals.

Benefits

• Equity
• Benefits

What This Job Offers

• Job Type: Full-time
• Career Level: Senior