Director, Cache RTL

Advanced Micro Devices, Inc•Fort Collins, CO

About The Position

AMD’s Cores Organization delivers CPUs, caches, and chiplets for its server, client, and gaming businesses. The Director, Cache RTL will lead the Cache Hierarchy RTL organization responsible for L2 and L3 cache designs in AMD’s next-generation CPU cores. The role combines senior technical leadership with people leadership, with ownership of microarchitecture, RTL implementation, and design quality from feature definition through tapeout across multiple concurrent programs and product generations. The director sets technical direction for high-performance, energy-efficient cache designs; makes and defends performance, power, area, and schedule trade-offs; and maintains high standards for design quality. The role includes leading managers and senior technical leads, scaling the organization, building and developing talent, and collaborating with architecture, physical design, verification, test, debug, and global product teams. The position is not eligible for visa sponsorship.

Requirements

Extensive experience leading RTL and microarchitecture teams, including managing managers, through multiple tapeouts of high-performance CPU, cache, or SOC designs to production silicon.
Deep expertise in cache architecture development and execution, including cache controller and array RTL implementation.
Strong command of digital RTL design, Verilog/SystemVerilog HDL, design-quality flows such as lint, CDC/RDC, and formal, and scripting.
Demonstrated ability to communicate clearly with executives and collaborate effectively with diverse teams across disciplines and geographies.
Multiple years of hardware design experience, including several years of people leadership.
Bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Science, Computer Engineering, or a similar field.

Nice To Haves

Experience with CPU coherency, coherent NOC, cache allocation and replacement policy, prefetch interaction, quality of service, fairness, and forward-progress architecture and implementation.
Experience with low-power design techniques and RAS features, including ECC, error detection, and handling in cache and memory subsystems.
Experience executing concurrent programs with shared or configurable IP and delivering IP to SOC and chiplet integration teams.

Responsibilities

Lead the functional L2 and L3 cache RTL teams, including first-line managers and senior technical leads, and own microarchitecture, RTL implementation, and design quality for the cache hierarchy.
Partner with Cache and CPU Architects to translate architecture into optimized microarchitecture and drive feature definition, scope, and performance, power, and area trade-offs across cache controllers, arrays, coherency, and routing fabric.
Own RTL execution across concurrent programs and product generations, including feature enablement plans, milestone commitments, staffing, schedules, and communication of status, risks, and mitigations to senior leadership.
Partner with Physical Design leadership to optimize RTL for physical construction, timing closure, and area, and ensure RTL releases support floorplan and tapeout milestones.
Partner with Design Verification leadership to ensure features are documented and verifiable, achieve high-confidence closure, and use objective design-quality metrics.
Partner with Design for Test and Debug teams to deliver reliable, testable, debuggable, and manufacturable RTL.
Work across global teams to resolve interactions among core, cache, and SOC/chiplet designs, and drive IP reuse and configurability across server, client, and gaming products.
Champion innovation in design methodology, automation, and AI-assisted engineering to simplify design complexity, improve quality, and increase productivity.
Recruit, develop, and retain engineering talent; mentor managers and technical leaders; build succession depth; and foster an inclusive, accountable team culture.
Represent the Cache Hierarchy RTL organization in cross-functional, program, and executive reviews, and create technical and program presentations for peers, partners, and management.