RTL Lead

Normal Computing Corporation • Palo Alto, CA

3d

About The Position

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry, critical AI infrastructure, and broader systems. The Lead RTL Design Engineer will lead and own digital logic design for Normal’s thermodynamic hardware, working across classical ASIC design, novel computing architectures, and integrated hardware-and-algorithm development.

The role owns RTL from microarchitecture through tapeout, including writing microarchitecture specifications, developing synthesizable SystemVerilog, collaborating with design verification on conventional and formal verification, and working with physical design to meet area and timing constraints. The Lead will help hire and organize the design team, refine design methodology, establish standards, and track progress against schedules. The position also contributes to architecture decisions and requires close coordination across architecture, verification, and physical design as specifications evolve.

Normal Computing works across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. The company is an Equal Opportunity Employer and provides reasonable accommodations to individuals with disabilities.

Requirements

• Experience leading an RTL design team through multiple tapeouts, including block-level and top-level work.
• Hands-on experience writing production RTL in SystemVerilog and closing designs through synthesis and place-and-route across multiple blocks and designs.
• Experience with datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging skills across simulation, waveforms, and formal counterexamples.
• Ability to work directly with architects and physical designers.
• Track record of driving key initiatives, energizing an RTL team, and fostering cross-functional alignment.
• Experience taking silicon through tapeout sign-off and active involvement in RTL implementation and design closure.

Nice To Haves

• Experience at an AI chip company where design and verification were tightly coupled.
• Experience with multiple interface architectures, such as PCIe, Ethernet, and memory devices.
• Familiarity with FPGAs.
• Experience using AI-assisted RTL or EDA tools in a design workflow.
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development.

Responsibilities

• Lead and organize the RTL design team, set standards and expectations, and foster a collaborative, execution-focused environment.
• Create and enforce RTL coding standards.
• Write and own synthesizable SystemVerilog RTL for datapath logic, control, and memory interfaces.
• Work with architecture to translate high-level specifications into implementable microarchitectures.
• Work with verification engineers to review verification plans, assist with debugging, and help close coverage.
• Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
• Participate in design reviews and contribute to architecture decisions.
• Support tapeout preparation, create tapeout criteria, sign off on tapeout readiness, and assist with post-silicon bring-up as needed.
• Help with hiring, refine design methodology, organize the design team around schedules, and track progress.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed