Hardware Engineer, RTL Lead

Normal Computing Corporation • Palo Alto, CA

5d

About The Position

As a Lead RTL Design Engineer at Normal, you will lead and own the design of digital logic for Normal's thermodynamic hardware. The work combines classical ASIC design, novel computing architectures, and an environment in which hardware and algorithms are developed together.

You will own RTL from microarchitecture through tapeout, including writing microarchitecture specifications, creating synthesizable SystemVerilog, partnering with design verification engineers to test designs using conventional and formal methods, and collaborating with physical design to meet area and timing constraints. As a Lead, you will also help with hiring, refine design methodology, organize the design team around schedules, and track progress. The role includes shaping architecture and making first-principles decisions for chips that are not standard accelerators.

The successful candidate will have a record of driving key initiatives, energizing an RTL team, and aligning architecture, verification, and physical design. They will have led silicon through tapeout sign-off, actively contributed to RTL implementation and design closure, and be comfortable working in a dynamic setting where system specifications evolve alongside architecture and design development.

Requirements

• Experience leading an RTL design team through multiple tapeouts, including block-level and top-level work.
• Hands-on experience writing production RTL in SystemVerilog and closing designs through synthesis and place-and-route across multiple blocks and designs.
• Experience with datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging skills across simulation, waveforms, and formal counterexamples.
• Ability to work directly with architects and physical designers.
• Track record of driving key initiatives and fostering cross-functional alignment across architecture, verification, and physical design.
• Experience leading silicon through tapeout sign-off and actively contributing to RTL implementation and design closure.

Nice To Haves

• Experience at an AI chip company where design and verification were tightly coupled.
• Experience with multiple interface architectures, such as PCIe, Ethernet, and memory devices.
• Familiarity with FPGAs.
• Experience using AI-assisted RTL or EDA tooling in a design workflow.
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development.

Responsibilities

• Organize the RTL design team, establish standards and high expectations, and foster a collaborative, execution-focused environment.
• Create and enforce RTL coding standards; write and own synthesizable SystemVerilog RTL for datapath logic, control, and memory interfaces.
• Work with architecture teams to translate high-level specifications into implementable microarchitectures.
• Partner with verification engineers to review verification plans, assist with debugging, and help close coverage.
• Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
• Participate in design reviews and contribute to architecture decisions.
• Support tapeout preparation, establish tapeout criteria, sign off on tapeout readiness, and assist with post-silicon bring-up as needed.
• Help with hiring, develop and refine design methodology, organize the design team around schedules, and track progress.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed