RTL Design Engineer

Voltai • Palo Alto, CA

1d

About The Position

Voltai is developing world models and agents to learn, evaluate, plan, experiment, and interact with the physical world, beginning with hardware, electronics systems, and semiconductors. In this role, you will design and own RTL for production silicon, from microarchitecture through signoff-ready code. You will work on real chip programs with leading semiconductor companies and help Voltai's AI learn to write, review, and debug RTL according to expert design practices.

Requirements

• At least 5 years of RTL design experience on chips that taped out.
• Expertise in SystemVerilog/Verilog and strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.
• Familiarity with common protocols such as AXI, PCIe, Ethernet, or DDR, or similar protocols.
• Python or Tcl scripting.

Nice To Haves

• Experience writing SVA or working with formal verification.
• Low-power design experience, including UPF, clock gating, and power gating.
• Interest in AI-assisted design tools.

Responsibilities

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL, and help define correct, high-quality design.
• Work directly with customer design teams when needed.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed