RTL Design Engineer

Delos Data Inc•Palo Alto, CA

17h•$160,000 - $240,000

About The Position

An experienced Senior RTL Design Engineer responsible for designing, implementing, and delivering high-quality RTL for complex digital systems. The role focuses on translating architectural specifications into scalable microarchitectures and production-ready RTL, with strong attention to performance, power, and area. The ideal candidate has deep hands-on experience with Verilog/SystemVerilog, strong digital design fundamentals, and experience across the full design lifecycle in collaboration with architecture, verification, and physical design teams.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of experience in RTL design.
Strong hands-on experience with Verilog/SystemVerilog.
Solid understanding of synchronous digital design and microarchitecture principles.
Experience with simulation and debug tools such as VCS, Questa, Verdi, or DVE.
Familiarity with synthesis, timing, and physical design constraints.
Strong analytical and problem-solving skills.
Clear written and verbal communication skills for cross-functional collaboration.
High attention to detail and ability to deliver high-quality design outcomes.
Ability to work independently and manage tasks to completion, including AI-assisted workflows.

Nice To Haves

Experience designing high-performance systems such as AI/ML accelerators, networking systems, or SoCs.
Familiarity with low-power design techniques such as clock gating and power gating.
Exposure to DFT concepts and design-for-test considerations.
Experience with scripting languages such as Python or Tcl.
Experience working in advanced semiconductor process nodes.
Experience using AI coding agents such as Claude Code, Cursor, or Copilot in RTL implementation, debugging, and timing-closure workflows, with rigor to verify AI-generated output.
Interest in turning design experience into reusable AI agent guidance, such as RTL coding patterns, timing-closure playbooks, or review checklists.

Responsibilities

Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
Translate architectural specifications into clean, efficient, and scalable microarchitectures.
Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure.
Develop high-quality, reusable RTL with strong coding standards and documentation.
Perform linting and CDC analysis, and ensure designs are synthesis-ready.
Support RTL integration and debugging in simulation and early silicon environments.
Participate in design reviews and provide technical input on architecture and implementation tradeoffs.
Work with verification teams to ensure comprehensive functional coverage.
Assist with timing closure and support backend teams as needed.
Contribute to continuous improvement of design methodologies, flows, and tools.