Senior ASIC Timing Engineer, DFT

NVIDIA•Santa Clara, CA

About The Position

NVIDIA is seeking a motivated DFT-Timing Engineer to join its dynamic and growing team. The role drives timing analysis and closure for DFT logic across NVIDIA chips—including GPUs, CPUs, DPUs, LPUs, and SoCs—at block, cluster, and full-chip hierarchical levels. The engineer collaborates with PD, DFX, Clocks, and other teams to establish timing-closure strategies, develop constraints for custom DFT designs, drive timing and power convergence, and implement ECOs. The role also works to improve workflows and designs through greater automation, resilience, and standardization.

Requirements

Bachelor’s degree or equivalent experience in Electrical or Computer Engineering and 5+ years of experience, or a master’s degree or equivalent experience and 2+ years of experience.
Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip or sub-chip level in advanced technology nodes.
Expertise in analyzing timing paths and fixing them through ECOs.
Expertise in developing timing constraints.
In-depth knowledge of industry-standard timing-convergence tools.

Nice To Haves

Understanding of DFT logic and experience with DFT timing closure in modes such as scan and iJTAG.
Background in domain-specific STA and timing convergence, such as Serdes, Processor, IO, or SMVA.
Experience in methodology and/or workflow development.

Responsibilities

Drive timing analysis and closure for DFT logic on NVIDIA chips, including GPUs, CPUs, DPUs, LPUs, and SoCs, at block, cluster, and full-chip levels.
Work with PD, DFX, Clocks, and other teams to establish timing-closure strategies.
Develop timing constraints for custom DFT designs.
Drive timing and power convergence and implement ECOs.
Improve workflows and designs through automation, resilience, and standardization.