ASIC DFT Engineer - Acacia (Hybrid)

Cisco•San Jose, CA

1d•Hybrid

About The Position

Acacia, part of Cisco, develops silicon-based high-speed optical interconnect products, including DSP ASICs, silicon photonic PICs, and coherent modules. This hybrid position can be performed three days per week from Cisco’s San Jose, California office. The DFT Engineer supports design-for-testability implementation, validation, and signoff for complex ASIC and SoC designs. The role works with senior DFT engineers and cross-functional teams spanning RTL design, verification, physical design, product engineering, and test to deliver test coverage and manufacturability for advanced semiconductor designs. Responsibilities include implementing and validating DFT features, running checks and ATPG flows, analyzing coverage and reports, debugging issues, supporting integration and silicon debug, and automating flows and reporting. The minimum qualification is a bachelor’s degree with 5 years of related experience, a master’s degree with 3 years, a Ph.D. with 0 years, or equivalent related work experience. The listed starting salary range is $155,000 to $222,600 for U.S. and/or Canada locations, excluding incentive compensation, equity, and benefits; salary varies by hiring location and qualifications. Cisco also lists location-specific salary ranges for certain U.S. locations. U.S. benefits, subject to eligibility and applicable policies, include medical, dental, and vision insurance; a 401(k) plan with matching contribution; paid parental leave; short- and long-term disability coverage; basic life insurance; paid holidays and other paid time away; and potential annual bonuses for non-sales roles. Eligible employees may also receive Cisco restricted stock units. Additional time-off provisions and incentive compensation details vary by employee classification and role.

Requirements

Bachelor’s degree and 5 years of related experience, master’s degree and 3 years of related experience, Ph.D. and 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation.
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls.
Experience with stuck-at and transition fault models.
Experience debugging DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures.
Scripting experience using Tcl, Python, Perl, or shell.

Nice To Haves

Experience with hierarchical DFT methodology and block-level signoff.
Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows.
Experience with MBIST insertion, memory test validation, or BISR flows.
Familiarity with gate-level simulation, SDF timing, and pattern validation.
Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug.
Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs.
Ability to improve automation, regression checks, and DFT reporting dashboards.
Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation.
Experience troubleshooting ASIC DFT problems and working with cross-functional teams.

Responsibilities

Support DFT implementation for ASIC and SoC blocks and subsystems.
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic.
Run DFT rule checks and debug scan, clock, reset, and test-mode issues.
Generate and validate ATPG patterns for stuck-at, transition, and other required fault models.
Analyze test coverage, pattern count, compression results, and ATPG reports.
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues.
Work with RTL and verification teams to ensure DFT requirements are correctly implemented.
Support block-level and full-chip DFT integration activities.
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable.
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting.
Support silicon debug, diagnosis analysis, and yield-learning activities as needed.
Document DFT implementation results, known issues, waivers, and signoff status.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays
Floating holiday for non-exempt employees
Paid day off for employee’s birthday
Paid year-end holiday shutdown
Personal wellness days
Paid vacation or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away for critical or emergency family issues
Optional paid volunteer days
Annual bonuses may be available for non-sales roles
Potential grants of Cisco restricted stock units