ASIC DFT Engineer - Acacia (Hybrid)

Cisco•San Jose, CA

3d•$155,000 - $222,600•Hybrid

About The Position

The ASIC DFT Engineer supports design-for-testability implementation, validation, and signoff for complex ASIC and SoC designs. The role works closely with senior DFT engineers and teams across RTL design, verification, physical design, product engineering, and test to deliver test coverage and manufacturability for advanced semiconductor designs. This is a hybrid role that can be performed three days per week from Cisco’s San Jose, California office.

Requirements

Bachelor’s degree and 5 years of related experience, or a master’s degree and 3 years of related experience, or a Ph.D. and no years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation.
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls.
Experience with stuck-at and transition fault models.
Experience debugging DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures.
Scripting experience using Tcl, Python, Perl, or shell.

Nice To Haves

Experience with hierarchical DFT methodology and block-level signoff.
Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows.
Experience with MBIST insertion, memory test validation, or BISR flows.
Familiarity with gate-level simulation, SDF timing, and pattern validation.
Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug.
Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs.
Ability to improve automation, regression checks, and DFT reporting dashboards.
Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation.
Scripting experience using Tcl, Python, Perl, or shell.
Experience troubleshooting ASIC DFT problems and working with cross-functional teams.

Responsibilities

Support DFT implementation for ASIC and SoC blocks and subsystems.
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic.
Run DFT rule checks and debug scan, clock, reset, and test-mode issues.
Generate and validate ATPG patterns for stuck-at, transition, and other required fault models.
Analyze test coverage, pattern count, compression results, and ATPG reports.
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues.
Work with RTL and verification teams to ensure DFT requirements are correctly implemented.
Support block-level and full-chip DFT integration activities.
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable.
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting.
Support silicon debug, diagnosis analysis, and yield-learning activities as needed.
Document DFT implementation results, known issues, waivers, and signoff status.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays
Floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
Personal wellness days
Paid vacation or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses for eligible non-sales employees
Potential Cisco restricted stock unit grants