Timing Engineer

Altera•San Jose, CA

1d•$100,000 - $110,000•Onsite

About The Position

Altera is seeking a Timing Engineer to join its Physical Design organization. The role supports timing analysis and closure for FPGA designs, collaborating with Timing, Physical Design, RTL Design, and Architecture engineers. The engineer will gain hands-on experience with static timing analysis (STA), timing constraints and reports, timing optimization, and closure methodologies. The position is suited to someone with a foundation in digital design and timing concepts who wants to develop expertise in semiconductor timing analysis and advanced FPGA design methods.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
At least 1 year of relevant experience in timing analysis, digital design, semiconductor engineering, VLSI, ASIC, FPGA, or a related technical field.
At least 1 year of experience or equivalent hands-on project experience with digital logic, digital circuits, computer architecture, or integrated circuit design.
At least 1 year of experience or coursework involving timing analysis, simulation, design verification, or related engineering analysis.
At least 1 year of experience or coursework using Linux/Unix environments and technical scripting with Python, Tcl, Perl, or similar languages.
Foundational understanding of digital timing concepts, setup and hold timing, clocking, and semiconductor design methodologies.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Experience with static timing analysis (STA), timing constraints, timing reports, or timing closure.
Familiarity with setup and hold analysis, clock skew, clock uncertainty, critical paths, timing slack, and timing exceptions.
Experience with Python, Tcl, Perl, or similar scripting languages for engineering automation and data analysis.
Familiarity with multi-corner/multi-mode (MCMM) timing analysis and process, voltage, and temperature (PVT) variations.
Experience with FPGA, ASIC, SoC, or semiconductor design projects through professional experience, academic research, or hands-on projects.
Familiarity with physical design concepts including synthesis, placement, routing, clock distribution, and design optimization.
Experience working in Linux/Unix environments and with software development or version-control tools.
Strong analytical and problem-solving skills and the ability to collaborate effectively across engineering teams.

Responsibilities

Support static timing analysis (STA) for block-level and subsystem-level designs.
Analyze timing reports to identify setup, hold, and other timing violations, and work with senior engineers to determine root causes.
Support the development, review, and validation of timing constraints for FPGA designs.
Analyze timing results across multiple operating conditions, process corners, and design modes.
Assist with timing closure by identifying critical paths and providing data-driven optimization recommendations.
Support timing optimization and engineering change order (ECO) activities under the guidance of experienced engineers.
Develop and maintain Python, Tcl, Perl, or similar scripts to automate timing analysis and improve engineering workflows.
Assist with running and analyzing large-scale timing data and generating reports for engineering teams.
Support timing budget analysis and help identify challenges at block and interface boundaries.
Work with Physical Design and RTL engineers to investigate timing issues and evaluate potential solutions.
Participate in timing methodology and flow improvements to increase efficiency, accuracy, and design quality.
Document timing analysis, results, and technical findings for design reviews and future development.
Develop familiarity with industry-standard timing analysis tools, methodologies, and semiconductor design flows.