Senior Static Timing Analysis (STA) Engineer

Intel Corporation•Santa Clara, CA

5d•$164,470 - $269,100•Hybrid

About The Position

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive the development of next-generation semiconductor products. In this role, you will play a critical part in delivering high-performance, power-efficient System-on-Chip (SoC) designs that power industry-leading technologies. You will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness. This position offers an exciting opportunity to solve complex engineering challenges while influencing methodologies and best practices used across advanced SoC programs.

Requirements

Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience.
5+ years of experience the following: SOC level static timing analysis, clock network design, and timing closure methodologies.
Timing constraint adaptation, physical design knowledge, and optimization techniques.
Industry-standard tools for timing analysis, extraction, and physical design.
TCL scripting and timing budgeting processes.

Nice To Haves

A PhD in the same filed and 2+ years of experience.
Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
Knowledge of tools, flows, and methodologies for high-performance physical design.
Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
DFT architecture knowledge is a strong plus.

Responsibilities

Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
Define methodologies to produce high-quality timing models and enable efficient physical design execution.
Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.