Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Altera Semiconductor•San Jose, CA

3d•Onsite

About The Position

You will be working in the Design Automation group for the technical owner of Static Timing Analysis flows and timing modeling methodology across Altera's ASIC, Custom and Semi-Custom IP designs — and the leader of the small team that delivers it. This role offers real architectural latitude as the team is in the middle of a genuine modernization: standing up next-generation characterization flows, and onboarding timing sign-off into a new unified flow environment. There is meaningful greenfield work here, not just incremental maintenance. The role provides breadth rarely found in one seat, spanning block-level, full-chip, transistor-level and FPGA timing collateral. Few timing DA roles span SPICE-level circuit simulation and cell characterization at one end through customer-facing FPGA timing deliverable flows at the other. You will represent the timing DA domain with design team leads, physical design, technology enablement and QRE partners in cross-functional methodology forums and working groups, and you will drive engagements with major EDA vendors — evaluating capabilities, escalating what blocks progress, and shaping roadmaps. Being the bridge between what designers need and what the tools can do is the heart of this role. It reports directly to the DA engineering director for the domain, so your technical judgment carries without layers of translation. This is a hands-on CAD role where you will develop and release production-grade flows, regressions and automation, then support the design teams running them — triaging tickets, debugging timing issues alongside designers on live tape-outs, and delivering the training and documentation that make the methodology stick. You will work alongside a small group of deep specialists whose domains span circuit simulation and optimization, custom cell characterization and Liberty model generation, FPGA timing model generation, and timing derate and reliability methodology. Being the technical lead means influencing the whole chain from transistor-level simulation through characterization to the timing models that design teams and the FPGA software toolchain ship — not just the analysis step in the middle. If you have ever wanted your timing decisions to reach all the way back into how the models are built, this is that seat. There is room to grow your own technical range, as you will set technical direction and mentor engineers on timing methodology. You should expect to learn as much from the characterization and circuit-simulation depth around you as you bring to it. You will also have a genuine voice in how the company invests in the timing domain going forward. The company is actively applying AI and ML inside its design automation flows — runtime and resource prediction, corner reduction, knowledge capture from debug. If you want to bring those techniques into timing, characterization or model generation, you will find an organization already leaning in.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field.
Significant hands-on experience developing and deploying production design automation or timing flows.
10+ years of experience working with Static Timing Analysis (STA) and timing sign-off methodology, including timing constraints, multi-corner multi-mode (MCMM) analysis, crosstalk, on-chip variation (OCV), timing derates, and advanced process-node timing challenges.
10+ years of experience with industry-standard timing analysis, cell characterization, and/or SPICE circuit simulation tools, with the technical depth to evaluate tool capabilities and make methodology decisions.
10+ years of experience developing automation and software for engineering workflows, including strong proficiency with Python, Tcl, shell scripting, or similar languages.
Solid understanding of algorithms, data structures, and production-quality software development practices.
Demonstrated experience owning and releasing production-grade DA/CAD flows, including flow architecture, regression infrastructure, automation, validation, deployment, maintenance, and user support.
Demonstrated technical leadership in a design automation or timing domain, including setting methodology direction, driving complex technical decisions, establishing best practices, and mentoring engineers without requiring formal management authority.
Proven experience partnering directly with ASIC, custom IC, physical design, circuit design, or other semiconductor design teams to define methodology requirements, deploy production flows, resolve technical issues, and support designs through tape-out or sign-off.
Demonstrated ability to lead cross-functional technical initiatives and influence engineering decisions across geographically distributed teams, including collaboration with design, physical design, technology/process, reliability, and EDA vendor organizations.
Eligibility for any required U.S. export authorizations.

Nice To Haves

Experience owning block-level and/or full-chip STA methodology and timing closure flows through multiple production tape-outs.
Advanced experience with cell characterization and Liberty model generation, including LVF, POCV, statistical timing, or related variation-aware modeling methodologies.
Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows.
Experience developing or supporting FPGA timing models, timing collateral, or customer-facing timing deliverables.
Experience with timing reliability, aging, derating, electromigration, or other reliability-aware timing methodologies.
Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off requirements.
Experience evaluating, deploying, and influencing roadmaps for major commercial EDA tools and vendors, including the ability to identify tool gaps and drive technical escalations.
Experience applying AI/ML techniques to design automation, including runtime/resource prediction, timing optimization, corner reduction, knowledge capture, or automated debug.
Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives across multiple engineering organizations.
Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

Responsibilities

Develop and release production-grade Static Timing Analysis (STA) flows, regressions, and automation.
Support design teams running STA flows, including triaging tickets and debugging timing issues on live tape-outs.
Deliver training and documentation to ensure methodology adoption.
Represent the timing DA domain in cross-functional methodology forums and working groups.
Drive engagements with EDA vendors, evaluating capabilities, escalating issues, and shaping roadmaps.
Set technical direction and mentor engineers on timing methodology.
Influence the entire timing chain from transistor-level simulation and characterization to timing model generation.
Apply AI/ML techniques to design automation flows, including timing, characterization, or model generation.