Staff Engineer, Static Timing Analysis CAD Engineer

Samsung Electronics•Austin, TX

5d•$151,000 - $226,600

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Staff Static Timing Analysis (STA) CAD Engineer, you will work on ensuring timing integrity and signoff readiness for Samsung’s next-generation GPU IPs used in premium smartphones and adjacent market segments. Your role will be working closely with design execution teams to ensure that they have the most effective and efficient flows possible, while innovating and developing cutting edge solutions for upcoming projects. In this mid-level individual contributor role, you will collaborate closely with Design and EDA partners to develop and implement automation and methodologies for timing analysis that ensure convergent strategies for complex advanced node designs. You bring curiosity, hands-on STA expertise, a solid understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure across functional and test modes. You provide creative solutions utilizing software and hardware expertise to support the needs of STA design teams with complex timing environments. You have a software first mentality and find satisfaction in using software to solve complex issues in elegant, scalable methods. You support STA teams by providing automation that simplifies execution, reduces mistakes, and maximizes user efficiency. You understand the details of the STA methodologies so that you can effectively test and debug unexpected issues that arise with new technology node bring up. You contribute to technical excellence by applying and help influencing STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices—including POCV, multi-corner analysis, and low-power constraints—to improve timing quality, convergence, and predictability. You take initiatives on moderate-to-complex projects, communicating openly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging technologies. You utilize AI in your work and apply it to improve your efficiency with your daily engineering tasks.

Requirements

6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
Working knowledge and experience with LLE, POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, StarRC, PrimeClosure, Tempus).
Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Python, Perl, Shell script.
Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment.

Responsibilities

Work on ensuring timing integrity and signoff readiness for Samsung’s next-generation GPU IPs used in premium smartphones and adjacent market segments.
Work closely with design execution teams to ensure that they have the most effective and efficient flows possible, while innovating and developing cutting edge solutions for upcoming projects.
Collaborate closely with Design and EDA partners to develop and implement automation and methodologies for timing analysis that ensure convergent strategies for complex advanced node designs.
Apply sound methodology and deliver high-quality timing closure across functional and test modes.
Provide creative solutions utilizing software and hardware expertise to support the needs of STA design teams with complex timing environments.
Support STA teams by providing automation that simplifies execution, reduces mistakes, and maximizes user efficiency.
Test and debug unexpected issues that arise with new technology node bring up.
Contribute to technical excellence by applying and help influencing STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices—including POCV, multi-corner analysis, and low-power constraints—to improve timing quality, convergence, and predictability.
Take initiatives on moderate-to-complex projects, communicating openly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging technologies.
Utilize AI in your work and apply it to improve your efficiency with your daily engineering tasks.