Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Altera•San Jose, CA

4d•$187,000 - $270,000•Onsite

About The Position

Altera is seeking a technical owner for Static Timing Analysis (STA) flows and timing modeling methodology across Altera's ASIC, Custom and Semi-Custom IP designs. This role involves leading a small team and driving the modernization of next-generation characterization flows and onboarding timing sign-off into a new unified flow environment. The position offers significant greenfield work and broad exposure across block-level, full-chip, transistor-level, and FPGA timing collateral. The individual will represent the timing DA domain in cross-functional forums, drive engagements with EDA vendors, and develop/release production-grade flows, regressions, and automation. This is a hands-on CAD role supporting design teams through tape-outs and providing training and documentation. The role also involves working alongside specialists in circuit simulation, cell characterization, Liberty model generation, and timing derate/reliability methodology. The technical lead will set direction, mentor engineers, and influence future investments in the timing domain. There is also an opportunity to apply AI and ML techniques within design automation flows.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field.
Significant hands-on experience developing and deploying production design automation or timing flows.
10+ years of experience working with Static Timing Analysis (STA) and timing sign-off methodology, including timing constraints, multi-corner multi-mode (MCMM) analysis, crosstalk, on-chip variation (OCV), timing derates, and advanced process-node timing challenges.
10+ years of experience with industry-standard timing analysis, cell characterization, and/or SPICE circuit simulation tools, with the technical depth to evaluate tool capabilities and make methodology decisions.
10+ years of experience developing automation and software for engineering workflows, including strong proficiency with Python, Tcl, shell scripting, or similar languages.
Solid understanding of algorithms, data structures, and production-quality software development practices.
Demonstrated experience owning and releasing production-grade DA/CAD flows, including flow architecture, regression infrastructure, automation, validation, deployment, maintenance, and user support.
Demonstrated technical leadership in a design automation or timing domain, including setting methodology direction, driving complex technical decisions, establishing best practices, and mentoring engineers without requiring formal management authority.
Proven experience partnering directly with ASIC, custom IC, physical design, circuit design, or other semiconductor design teams to define methodology requirements, deploy production flows, resolve technical issues, and support designs through tape-out or sign-off.
Demonstrated ability to lead cross-functional technical initiatives and influence engineering decisions across geographically distributed teams, including collaboration with design, physical design, technology/process, reliability, and EDA vendor organizations.
Eligibility for any required U.S. export authorizations.

Nice To Haves

Experience owning block-level and/or full-chip STA methodology and timing closure flows through multiple production tape-outs.
Advanced experience with cell characterization and Liberty model generation, including LVF, POCV, statistical timing, or related variation-aware modeling methodologies.
Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows.
Experience developing or supporting FPGA timing models, timing collateral, or customer-facing timing deliverables.
Experience with timing reliability, aging, derating, electromigration, or other reliability-aware timing methodologies.
Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off requirements.
Experience evaluating, deploying, and influencing roadmaps for major commercial EDA tools and vendors, including the ability to identify tool gaps and drive technical escalations.
Experience applying AI/ML techniques to design automation, including runtime/resource prediction, timing optimization, corner reduction, knowledge capture, or automated debug.
Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives across multiple engineering organizations.
Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

Responsibilities

Provide real architectural latitude in the modernization of next-generation characterization flows and onboarding timing sign-off into a new unified flow environment.
Gain breadth of experience across block-level, full-chip, transistor-level, and FPGA timing collateral.
Represent the timing DA domain in cross-functional methodology forums and working groups with design team leads, physical design, technology enablement, and QRE partners.
Drive engagements with major EDA vendors, evaluating capabilities, escalating issues, and shaping roadmaps.
Develop and release production-grade flows, regressions, and automation.
Support design teams running production flows, including triaging tickets and debugging timing issues on live tape-outs.
Deliver training and documentation to ensure methodology adoption.
Influence the entire chain from transistor-level simulation through characterization to the timing models shipped with design teams and the FPGA software toolchain.
Set technical direction and mentor engineers on timing methodology.
Apply AI and ML techniques to design automation flows, such as runtime and resource prediction, corner reduction, knowledge capture from debug, and bringing these techniques into timing, characterization, or model generation.