Senior ASIC Physical Design Engineering Technical Lead

Cisco•San Jose, CA

About The Position

The Senior ASIC Physical Design Engineering Technical Lead will contribute to Cisco’s Silicon One team, which develops silicon and hardware platforms for switching, routing, and wireless products. The position focuses on RTL-to-GDSII implementation and methodology, optimizing performance and die size across the physical design flow. The role also works with RTL, DFT, implementation, EDA vendors, and tool and flow teams to improve design methodologies and support full-chip development.

Requirements

Bachelor’s degree in Electrical Engineering and 12+ years of Physical Design experience, or a Master’s degree in Electrical Engineering and 8+ years of Physical Design experience, or a PhD in Electrical Engineering and 5+ years of Physical Design experience.
Experience working on full-chip activities.
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
Experience with EDA tools such as Innovus, PrimeTime/Tempus, Redhawk/Voltus, and Calibre.

Nice To Haves

Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
Experience with static timing analysis concepts, defining timing constraints and exceptions, and corners/voltage definitions.
Experience in full-chip floor-planning and power grid planning.
Experience with custom clock (H-Tree or Mesh) at chip level.
Experience with Python, TCL, or Perl programming.

Responsibilities

Perform RTL-to-GDSII implementation, including logic synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks, with a focus on performance and die-size optimization.
Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative enhancements.
Collaborate with RTL, DFT, implementation, EDA vendors, and tool and flow teams to enable best-in-class design methodology.
Guide Clock Tree Synthesis (CTS) strategies and provide actionable feedback to implementation teams.
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
Complete functional and timing ECO implementation using industry-standard flows and contribute to STA methodology automation.
Evaluate timing methodologies and tools across different technologies and design types.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility rules.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
10 paid holidays per full calendar year, plus one floating holiday for non-exempt employees.
One paid day off for an employee’s birthday, paid year-end holiday shutdown, and four paid personal wellness days.
Non-exempt employees receive 16 days of paid vacation per full calendar year; exempt employees participate in a flexible vacation time-off program with no defined limit, subject to availability and business limitations.
80 hours of sick time off provided on hire date and each January 1 thereafter, with up to 80 unused hours carried forward from one calendar year to the next.
Additional paid time away may be requested for critical or emergency issues involving family members.
Optional 10 paid volunteer days per full calendar year.
Non-sales employees may be eligible for annual bonuses subject to Cisco policies.
Employees may be eligible for Cisco restricted stock unit grants, subject to vesting and continued employment.