ASIC Physical Design Technical Lead

Cisco•San Jose, CA

2d•$186,900 - $267,700

About The Position

Cisco’s Common Hardware Group develops hardware platforms for switching, routing, and wireless products, including silicon, optics, and platforms such as Silicon One. The ASIC Physical Design Technical Lead will contribute to full-chip physical design and RTL-to-GDSII implementation, optimizing performance, power, and die size. The role works across system and package design, RTL, DFT, implementation, EDA vendors, tool and flow teams, foundries, and standard-cell IP vendors. It also involves improving design flows and methodologies, supporting signoff practices, and using AI tools to improve productivity.

Requirements

Bachelor’s degree in Electrical Engineering and at least 8 years of physical design experience; or a Master’s degree in Electrical Engineering and at least 6 years; or a PhD in Electrical Engineering and at least 3 years.
Experience with full-chip activities.
Experience with RTL-to-GDSII flows and design tapeouts in 7 nm, 5 nm, 3 nm, or smaller process technologies.
Experience with EDA tools such as Innovus, Tempus or PrimeTime, Redhawk or Voltus, or Calibre or Pegasus.

Nice To Haves

Experience with hierarchical design, timing closure, physical-design convergence, and power-integrity analysis.
Experience with static timing analysis concepts, defining timing constraints and exceptions, and defining corners and voltage.
Experience with full-chip floorplanning and power-grid planning.
Experience with custom chip-level clock structures, such as H-tree or mesh.
Experience with Python and using AI tools through accurate prompting.
Hands-on experience with full-chip clock mesh and Flex-HTree methods.

Responsibilities

Develop full-chip floorplans based on design architecture, foundry integration guidelines, and IP placement constraints.
Collaborate with system and package design teams to understand requirements and incorporate them into the full-chip floorplan.
Perform hierarchical implementation, including partitioning, pin assignment, clock planning, and bump planning.
Implement RTL-to-GDSII flows, including floorplanning, power-grid planning, place and route, static timing analysis, power integrity, physical verification, and equivalence checks, with a focus on performance, power, and die-size optimization.
Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative improvements.
Work with RTL, DFT, implementation, EDA vendors, and tool and flow teams to enable design methodologies.
Apply low-power design methodologies using UPF.
Work with foundries and standard-cell IP vendors to define signoff methodologies and validate or adjust them in response to feedback from post-silicon validation teams.
Use AI tools to improve productivity.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued-employment vesting conditions.
Paid holidays and a floating holiday for non-exempt employees
Birthday day off, year-end holiday shutdown, and personal wellness days
Vacation time or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses may be available for non-sales roles, subject to Cisco policies.