Physical Design Technical Lead, ASIC, TPU

Google•Sunnyvale, CA

1d•$192,000 - $278,000

About The Position

Be part of a team developing custom silicon solutions for Google’s direct-to-consumer products. The role provides technical leadership for physical design of next-generation AI silicon, including Google Tensor Processing Units (TPUs). The scope is dynamic and may range from owning highly complex, critical macro-subsystems to leading project-wide top-level implementation, depending on project needs. The AI and Infrastructure team delivers AI and infrastructure at scale, efficiency, reliability, and velocity for Google users and customers. The role contributes to the physical design of complex silicon, balancing performance, power, and integration while driving end-to-end execution. The US salary range is $192,000–$278,000, with a 20% bonus target, equity, and benefits. Individual pay is determined by job-related skills, experience, and relevant education or training.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
Experience with Python, Tcl, or Perl scripting.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, and understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
Understanding of performance, power, and area trade-offs, and knowledge of DFT, including Scan, MBIST, and LBIST.
Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and communicate complex technical challenges clearly to stakeholders.

Responsibilities

Lead physical design implementation and strategy for high-performance silicon, from critical, complex subchips to top-level execution as project phases and team needs require.
Manage the full design cycle from RTL to GDSII, including sign-off closure for timing, electrical performance, and power integrity.
Partner with RTL, DFT, methodology, and packaging teams to achieve power, performance, and area (PPA) goals, including feasibility studies for new microarchitectures and RTL-run optimization.
Collaborate with external EDA and IP vendors to improve flows and methodologies, and contribute to internal processes for efficient, predictable execution.
Drive execution schedules, resource planning, and risk mitigation for the area of ownership, scaling leadership to support project-wide milestones.