Physical Design Lead, ASIC

Google•Sunnyvale, CA

1d•$192,000 - $278,000

About The Position

The Physical Design Lead will help develop custom silicon for Google's TPU technology, which powers AI/ML applications. The role focuses on physical design and implementation of custom datapaths and matrix multiplication accumulator blocks, from RTL through GDSII and final physical signoff. The lead will analyze performance, power, and area tradeoffs; develop implementation methodologies for complex arithmetic pipelines; and guide a small engineering team through sub-chip execution and delivery.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in physical design, including custom structured datapath implementation.
Experience hardening dense compute units, such as dot-product engines, MACs, multipliers, or ALUs, into high-frequency, low-power macros.
Experience with sub-7nm process nodes, including FinFET and Gate-All-Around architectures, and managing physical density and routing congestion in custom datapaths.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture.
Experience with structured placement methodologies, such as relative placement, data-flow-driven layout, and customized power-grid stitching for dense blocks.
Experience with logic synthesis, place-and-route, timing analysis, and physical and electrical design-check tools; familiarity with schematics, layout, and circuit or logic simulation tools.
Experience with physical design and timing, including managing PrimeTime-to-PnR timing correlations and metal-fill impacts on dense structures.
Expert-level scripting versatility in Tcl, Python, and Perl to build layout automation and structural constraints within standard EDA tools.

Responsibilities

Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL to GDSII, including synthesis, floor-planning, place and route, timing closure, and physical signoff.
Analyze math-intensive micro-architecture and conduct feasibility studies, evaluating performance, power, and area tradeoffs to achieve design closure.
Develop and improve physical design methodologies and customized implementation recipes to optimize PPA across complex arithmetic pipeline structures.
Manage physical design tools, including Synopsys Fusion Compiler, Cadence Innovus and Genus, PrimeTime, StarRC, Calibre, and Apache RedHawk.
Execute floor-planning, synthesis, placement, clock tree synthesis, timing closure, routing, extraction, physical verification, and final signoff, including DRC/LVS and EM/IR checks.
Lead sub-chip execution and delivery, providing technical guidance and mentorship to a small engineering team to support on-schedule project completion.