Senior ASIC Physical Design Engineering Technical Lead
About The Position
The Silicon One team develops hardware platforms that power Cisco’s switching, routing, and wireless products. This role leads ASIC physical design implementation from RTL to GDSII, with a focus on performance and die-size optimization. The work spans synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks. The role also improves design tools and methodologies, collaborates with RTL, DFT, implementation, EDA vendor, and flow teams, and guides clock-tree synthesis strategies. It includes STA setup, timing convergence and sign-off across multi-mode, multi-corner scenarios, functional and timing ECO implementation, and evaluation of timing methodologies and tools across technologies and design types.
Requirements
- Bachelor’s degree in Electrical Engineering and 12+ years of Physical Design experience, or a master’s degree in Electrical Engineering and 8+ years, or a PhD in Electrical Engineering and 5+ years.
- Experience working on full-chip activities.
- Experience with RTL-to-GDSII flows and design tapeouts in 7nm, 5nm, 3nm, or smaller process technologies.
- Experience with EDA tools such as Innovus, PrimeTime or Tempus, RedHawk or Voltus, and Calibre.
Nice To Haves
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis concepts, defining timing constraints and exceptions, and corner and voltage definitions.
- Experience in full-chip floorplanning and power-grid planning.
- Experience with custom chip-level clock structures such as H-tree or mesh.
- Experience with Python, TCL, or Perl programming.
Responsibilities
- Perform RTL-to-GDSII implementation, including logic synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks, optimizing performance and die size.
- Analyze tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative improvements.
- Collaborate with RTL, DFT, implementation, EDA vendors, and tool and flow teams to enable design methodology.
- Guide Clock Tree Synthesis strategies and provide actionable feedback to implementation teams.
- Execute STA setup, convergence methodologies, and sign-off across multi-mode, multi-corner scenarios.
- Implement functional and timing ECOs using industry-standard flows and contribute to STA methodology automation.
- Evaluate timing methodologies and tools across technologies and design types.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays and floating holiday for non-exempt employees
- Birthday day off, year-end holiday shutdown, and personal wellness days
- Paid vacation or flexible vacation time off, depending on employee classification
- Paid sick time
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses for eligible non-sales employees
- Potential Cisco restricted stock unit grants
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What This Job Offers
Job Type
Full-time
Career Level
Senior
