ASIC DFT Engineering Technical Leader

Cisco•San Jose, CA

About The Position

Join Cisco’s Silicon One development organization as an ASIC Implementation Technical Lead focused primarily on Design-for-Test (DFT). You will collaborate with front-end RTL and backend physical design teams to understand chip architecture and establish DFT requirements early in the design cycle. The role contributes to developing next-generation networking chips and leads DFT and quality processes throughout the implementation flow and post-silicon validation phases, with additional exposure to physical design signoff activities. You will also work with ATE engineers on pattern translation and validation.

Requirements

Bachelor’s degree in Electrical or Computer Engineering and 8+ years of experience, or a Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or a PhD in Electrical Engineering or Computer Engineering and 3+ years of experience.
Prior experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, or similar tool sets.
Prior experience with gate-level simulation, including timing-based simulations with SDF, and debugging with VCS and other simulators.
Prior post-silicon validation and debug experience.
Prior experience with scan insertion.

Nice To Haves

Verilog design experience, including developing custom DFT logic and IP integration; familiarity with functional verification.
Prior experience with EDA tools such as Tessent.
Prior experience with JTAG protocols (P1500, P1687).
Prior experience with SSN.
Scripting skills in Tcl, Python, or Perl.
Prior experience developing test static timing analysis constraints and achieving timing closure.

Responsibilities

Work with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
Help develop next-generation networking chips.
Lead DFT and quality processes throughout the implementation flow and post-silicon validation phases.
Work with ATE engineers on pattern translation and validation.
Participate in physical design signoff activities.

Benefits

Medical, dental, and vision insurance.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
A paid day off for employees’ birthdays.
Paid year-end holiday shutdown.
Paid personal wellness days.
Paid vacation time for non-exempt employees; exempt employees participate in a flexible vacation time-off program with no defined limit, subject to availability and business limitations.
Sick time off, including carryover of unused sick time subject to the stated limits.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Employees may be eligible for Cisco restricted stock unit grants.
Employees in non-sales roles are eligible to earn annual bonuses, subject to Cisco policies.