ASIC Engineering Technical Leader

Cisco • San Jose, CA

4d

About The Position

The ASIC Engineering Technical Leader will work on Cisco’s Silicon One Optics team, which develops hardware platforms and silicon for switching, routing, wireless, and optical products. The role focuses on physical design for next-generation 800G, 1.6T, and multi-terabit optical transceivers and driver ICs used in hyperscale AI/ML data centers.

The position leads end-to-end RTL-to-GDSII physical design implementation across advanced technology nodes, including hierarchical floorplanning, mixed-signal macro placement, and signoff. It also develops and scales implementation methodologies and automation, and leads physical execution and timing closure in collaboration with RTL, Analog, DFT, Packaging, and CAD teams.

Requirements

• Bachelor’s degree and 8 years of related experience, or a master’s degree and 6 years of related experience, or a Ph.D. and 3 years of related experience.
• Prior experience in ASIC/SoC physical design and implementation in advanced technology nodes.
• Hands-on experience with the full physical design flow at block and/or chip level.
• Hands-on expertise in EDA tool flows and back-end signoff criteria.
• Experience automating workflows with Python, TCL, and Shell scripts to maximize turnaround time and execution efficiency.

Nice To Haves

• Experience closing designs with high-speed, high-density, macro-dominant, and I/O-cell-intensive blocks.
• Expertise in STA methodology, SDC timing-constraint creation and analysis, and timing ECO generation for final signoff timing closure.
• Strong physical design fundamentals and the ability to identify, debug, and fix electromigration, IR-drop, RC parasitic extraction, and crosstalk/glitch violations.
• Hands-on experience with functional equivalence checking and functional ECOs.
• Experience in power-grid design and optimization.
• Good understanding of standard-cell IP and memory compiler IP.
• Experience integrating mixed-signal designs.

Responsibilities

• Lead end-to-end RTL-to-GDSII physical design implementation across advanced technology nodes.
• Drive hierarchical floorplanning, complex mixed-signal macro placement, and signoff for first-pass silicon success.
• Architect and scale digital implementation flows using custom TCL and Python automation and EDA vendor partnerships.
• Improve quality of results, turnaround time, and team-wide productivity.
• Lead physical execution across place and route, clock-tree synthesis, MMMC timing closure, and ECO iterations.
• Collaborate with RTL, Analog, DFT, Packaging, and CAD teams to resolve cross-domain design bottlenecks.

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• 401(k) plan with Cisco matching contribution
• Paid parental leave
• Short- and long-term disability coverage
• Basic life insurance
• Paid holidays
• Floating holiday for non-exempt employees
• Paid day off for employee’s birthday
• Paid year-end holiday shutdown
• Paid personal wellness days
• Vacation time or flexible vacation time off, depending on employee classification
• Sick time
• Additional paid time away may be requested for critical or emergency family issues
• Optional paid volunteer days
• Annual bonuses for eligible non-sales employees
• Potential Cisco restricted stock unit grants

What This Job Offers

• Job Type: Full-time
• Career Level: Senior