About The Position

Client is searching for a Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to continue driving next generation AI designs. This position will require in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out.

Requirements

  • TCL/PERL Scripting
  • Proficiency in related EDA Tools
  • Full physical design cycle experience: RTL to Tape-out
  • Excellent verbal and written communication skills
  • Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering
  • 8+ Years of relevant experience

Nice To Haves

  • in-depth experience in top-level STA EM/IR Analysis
  • in-depth experience in top-level floorplanning

Responsibilities

  • Execution of Physical Design, Physical Verification, and Timing Closure
  • Timing closure through various methods and strategies; preferable in-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
  • Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
  • Flow and Methodology Development
  • Collaborating with IC Design RTL Engineers
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