Principal Engineer, Physical Design (ASIC Place & Route) (San Jose, CA) (7429)

TSMC•West Covina, CA

4d•$140,000 - $220,000•Hybrid

About The Position

As a Principal Physical Design Engineer at TSMC Technology, Inc., you will lead end-to-end netlist-to-GDSII implementation for large, high-performance computing and AI silicon architectures. The role covers block- and chip-level execution, from synthesis and floorplanning through placement, clock tree synthesis, routing, optimization, and final signoff, with a focus on achieving power, performance, and area goals on advanced process nodes. Based at the San Jose Center of Excellence, you will work closely with customer partners and cross-functional architecture, CAD, and DFT teams to advance physical design methods and address complex physical and electrical challenges. The position follows a hybrid collaboration model requiring four days on-site, with regular work at customer partner facilities across the South Bay Area.

Requirements

Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Microelectronics, or a closely related technical field.
At least 10 years of hands-on experience in full-chip or block-level physical design implementation and signoff, with successful tapeouts.
Mastery of industry-standard EDA tools, such as Synopsys Fusion Compiler/ICC2, PrimeTime, and StarRC; Cadence Innovus, Tempus, and Voltus; or Siemens Calibre.
Experience implementing designs in TSMC N16/N12 or below, with deep knowledge of advanced FinFET parasitic extraction, multi-patterning, and variability effects.
Proficiency in Tcl, Perl, and/or Python for constructing, maintaining, and debugging automation pipelines and signoff scripts.
Strong communication and cross-functional leadership skills.
Flexibility to work regularly on-site and at customer partner facilities across the South Bay Area.

Nice To Haves

Hands-on physical design and tapeout experience on advanced FinFET/GAA nodes such as TSMC N5, N4, N3, or below.
Advanced knowledge of low-power methodology, including multi-voltage domains, dynamic/static power gating (UPF/CPF), and retention strategies.
In-depth understanding of advanced timing signoff, including POCV, advanced OCV, and hyper-convergent signoff flows.
Experience leading cross-functional task forces through tapeout milestones and complex foundry-interface debug cycles.

Responsibilities

Drive full-flow RTL/netlist-to-GDSII physical implementation for complex, multi-million-gate blocks, including synthesis, floorplanning, placement, clock tree synthesis, routing, and final signoff.
Create optimized floorplans, establish power delivery networks, and minimize congestion, channel utilization, and macro placement overhead.
Develop customized, low-skew, variation-aware clock tree architectures to maximize frequency margins within power budgets.
Perform advanced timing closure and post-route optimization, including functional and timing engineering change orders across multi-corner, multi-mode scenarios.
Lead analyses of signal electromigration, dynamic cross-talk noise, and power rail integrity/IR drop to meet reliability targets.
Direct physical verification signoff by debugging and resolving DRC, LVS, ERC, and antenna violations in alignment with foundry design rules.
Develop automation frameworks and design methodology improvements using Tcl and Python and/or Perl to improve tapeout velocity and cross-project PPA predictability.