Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA•Santa Clara, CA

10d•$136,000 - $264,500

About The Position

As a member of the CPU Cache Coherent Interconnects Design Team, the Senior ASIC Physical Design Engineer is responsible for the physical design of CPU on-chip interconnect networks and last-level caches. The work includes implementation, synthesis, and timing closure, in close collaboration with the logic design team on microarchitecture definition and feasibility. The role contributes to products spanning consumer graphics, self-driving cars, and artificial intelligence. The engineer is responsible for synthesis and achieving timing, area, performance, and power goals for on-chip interconnect networks and last-level caches, and helps evaluate the physical design of next-generation coherent interconnects and system-level caches.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
At least 5 years of experience in processor or other related high-performance semiconductor designs.
Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, and floor-planning.
In-depth knowledge of industry-standard physical design tools.
Strong communication and interpersonal skills.
Ability to work in a dynamic, global team.

Nice To Haves

Experience in interconnect, cache, or core design.
Verilog expertise.
Deep understanding of ASIC design flow, including RTL design and verification, DFT, and ECO.

Responsibilities

Perform physical design of CPU on-chip interconnect networks and last-level caches.
Work on implementation, synthesis, and timing closure.
Collaborate with the logic design team on microarchitecture definition and feasibility.
Synthesize designs and achieve timing, area, performance, and power goals for on-chip interconnect networks and last-level caches.
Help evaluate physical design for next-generation coherent interconnects and system-level caches.