RTL Intern

quadric • Burlingame, CA

14h • Onsite

About The Position

Quadric is hiring an RTL Intern to support development of its GPNPU system-on-chip (SoC) platform. The intern will work alongside the hardware team on SoC subsystem development, third-party IP integration, and power, performance, and area (PPA) optimization. The role offers hands-on exposure to front-end design and integration methodologies, low-power digital design, and timing closure, with opportunities to work directly with SoC architects and designers.

Quadric prefers the internship to be based onsite at its downtown Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period and available to work onsite. The position is temporary and pays $50–$57 per hour, depending on factors including role level, experience, skills, and competencies. Interns receive mentorship, meaningful project ownership, and hands-on experience working with industry experts in AI and semiconductor technology. The office provides catered lunch each day and is near shops, cafes, and local amenities.

Requirements

• Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficiency in SystemVerilog or Verilog.
• Ability to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated problem-solving and debugging capability, and clear technical communication.

Nice To Haves

• Coursework or project experience with computer architecture, low-power design, or RTL design.
• Exposure to logic synthesis, FPGA design, or performance modeling.
• Familiarity with scripting languages such as Python and using LLMs to get things done.

Responsibilities

• Support the design and integration of SoC-level subsystems, working alongside engineers integrating third-party IP such as NoC, PCIe/UCIe interfaces, DDR, and security.
• Contribute to documentation of SoC architecture and application requirements.
• Assist in analyzing and optimizing power, performance, and area (PPA) at the SoC level.
• Gain exposure to low-power digital design techniques and timing closure across front-end stages.
• Collaborate with SoC architects and designers to understand design intent and integration requirements.
• Communicate findings, blockers, and technical questions clearly to the team.

Benefits

• Hands-on experience working alongside industry experts in AI and semiconductor technology.
• Mentorship and meaningful project ownership from day one.
• Catered lunch each day in the office.
• Downtown Burlingame office location close to shops, cafes, and local amenities.

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: No Education Listed