CAD RTL/FE Manager

Apple

About The Position

As a manager in Apple’s RTL/FE CAD team, you will lead a team of approximately 20 CAD engineers developing software solutions used by RTL design and integration engineers across Apple chip families. The role combines RTL/front-end design-flow expertise, modern software engineering, people leadership, and transformation of engineering methodology. You will guide the team and partner organizations in adopting agentic workflows and agile, AI-assisted design practices to increase design velocity, reduce manual bottlenecks, and improve quality and sign-off readiness. You will oversee tools and services spanning RTL connectivity, SoC assembly, IP packaging, static sign-off checks such as Lint, CDC, and RDC, cloud-native services, and CI/CD pipelines. You will own the architecture and execution of the LLM harness for RTL/FE flows and establish benchmarks for workflow accuracy and autonomy. You will also set strategic roadmaps aligned with tapeout milestones, work with design and integration leads to address evolving challenges, and partner with EDA vendors on escalations and tool roadmaps. The position calls for demonstrated leadership in agentic systems, AI-augmented engineering, or agile hardware transformation.

Requirements

7+ years of experience as a people manager leading engineering teams.
BSc/MSc in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
Proven track record in RTL design, design integration, or RTL/FE CAD across complex SoC projects.
Strong software engineering foundation, including system architecture, algorithms, data structures, and modern software design principles.
Demonstrated experience driving workflow automation, process modernization, or agile transformation within hardware/CAD environments.
Outstanding communication, collaboration, and stakeholder management skills, with the ability to influence cross-functional technical direction.
Solid grasp of front-end chip design flows, including SystemVerilog/Verilog, RTL integration, static checks (Lint, CDC, RDC), synthesis, and simulation.
Prior expertise designing, deploying, or evaluating agentic workflows, LLM harnesses, or AI-assisted development tools in hardware design or software engineering.
Experience pioneering agile methodologies in silicon design, such as continuous integration for hardware, rapid iteration cycles, and automated regressions.
Hands-on experience with production RTL connectivity tools and SoC top-level assembly flows.
Strong modern Python expertise, including AsyncIO, FastAPI, Pydantic, and SQLAlchemy, and experience building distributed, cloud-native backend services.
Proven success managing relationships with major EDA vendors and driving large-scale tool adoption.

Responsibilities

Lead, mentor, and grow a team of approximately 20 CAD engineers, including talent acquisition, technical mentorship, performance management, and career development.
Drive adoption of agentic workflows and modern agile methodologies across the team and broader RTL/FE community.
Own the architecture and execution of the LLM harness for RTL/FE flows, including agentic tooling such as autonomous violation triage, intelligent connectivity synthesis, and design-assist agents.
Establish benchmarks to evaluate and improve workflow accuracy and autonomy.
Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Define strategic roadmaps and near-term execution plans aligned with tapeout milestones and organizational goals.
Collaborate with RTL design and integration leads to turn design challenges into software solutions.
Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Promote software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure.