FE Engineer

Apple • Cupertino, CA

3d • $150,400 - $225,300

About The Position

Apple Inc. is hiring an FE Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role covers micro-architecture development and specification, from early high-level architectural exploration and micro-architectural research through detailed specification. The engineer develops, assesses, and refines RTL designs to meet power, performance, area, and timing goals, and explores high-performance strategies with the performance verification team.

The position works with multifunctional engineering teams to implement and verify physical design for timing, area, reliability, testability, and power. It involves implementing CPU design modules, exploring micro-architectural features with architects, and making RTL changes to evaluate feature feasibility. The engineer also supports verification through test bench development, formal methods, and simulation/emulation, and works with design verification to make modifications that ensure functional correctness. Other work includes identifying power-hungry hardware blocks for power reduction and collaborating with Physical Design to reduce timing pressure and achieve timing closure. The schedule is 40 hours per week.

The base pay range is $150,400–$225,300 per year. Apple employees may participate in discretionary stock programs, including restricted stock unit awards and an Employee Stock Purchase Plan. Benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain education expenses, including tuition, for formal education related to career advancement. The role may also be eligible for discretionary bonuses or commission payments and relocation.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering or a related field.
• Experience and/or education using Verilog to create high-quality functional RTL that meets power, performance, and area requirements.
• Advanced computer architecture knowledge for designing state-of-the-art CPUs.
• VLSI knowledge applied to improving CPU frequency, power, and area.
• Knowledge of out-of-order superscalar processor techniques for CPU design.
• Knowledge of advanced branch prediction techniques to improve CPU branch predictors and performance.
• Knowledge of cache hierarchies and how to enhance CPU cache performance.
• Modeling skills in C++, Python, and Perl to develop performance and power concepts.
• Knowledge of power-performance curves and techniques for evaluating and improving them through low-power, high-performance architectures.
• CPU architecture knowledge for developing power models to evaluate next-generation CPU trade-offs.
• Knowledge of CPU workloads and characteristics, including code footprint, data footprint, and usage, to evaluate power, performance, and area trade-offs and tailor a CPU to target consumers.

Responsibilities

• Develop micro-architecture and specifications, from high-level architectural exploration and micro-architectural research through detailed specifications.
• Develop, assess, and refine RTL designs to meet power, performance, area, and timing goals.
• Explore high-performance strategies and work with the performance verification team to verify that RTL meets performance targets.
• Work with multifunctional engineering teams to implement and verify physical design for timing, area, reliability, testability, and power.
• Implement CPU design modules that meet performance and power goals.
• Use debugging skills and knowledge of C/C++ and Perl to support scripts and feature exploration.
• Support verification teams with test bench development, formal methods, and simulation/emulation for formal verification.
• Work with the Design Verification team to make required modifications and ensure designs are functionally correct.
• Explore performance features by developing micro-architectural ideas with architects and implementing raw RTL changes to assess feasibility.
• Identify power-hungry hardware blocks and reduce their power consumption through micro-architectural changes with minimal performance impact.
• Collaborate with the Physical Design team to reduce timing pressure and achieve timing closure.

Benefits

• Comprehensive medical coverage
• Dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain education expenses, including tuition, for formal education related to career advancement
• Opportunity to participate in discretionary restricted stock unit awards
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan
• Potential eligibility for discretionary bonuses or commission payments
• Potential relocation

What This Job Offers

• Job Type: Full-time