FE Engineer

Apple • Cupertino, CA

2d • $150,400 - $225,300

About The Position

Apple Inc. is hiring an FE Engineer to perform CPU micro-architecture development, from early architectural exploration and research through detailed specification. The role develops, assesses, and refines RTL designs to meet power, performance, area, and timing goals, and explores high-performance strategies with the performance verification team.

The engineer implements CPU design modules and works with multifunctional engineering teams on physical design considerations, including timing, area, reliability, testability, and power. The position supports verification through testbench development, formal methods, simulation and emulation, and design changes to ensure functional correctness. It also explores proposed micro-architectural features, identifies power-hungry hardware blocks for optimization, and collaborates with the Physical Design team on timing closure.

The position is based in Cupertino, California, and various unanticipated locations throughout the USA. The work schedule is 40 hours per week. The base pay range is $150,400–$225,300 per year, depending on skills, qualifications, experience, and location. Apple offers eligible employees benefits and compensation programs, including medical and dental coverage, retirement benefits, discounted products and services, education expense reimbursement for certain career-related formal education, potential discretionary bonuses or commissions, and possible relocation. Employees may also be eligible for discretionary restricted stock unit awards and may purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan. Program eligibility and terms apply.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering or a related field.
• Experience and/or education utilizing Verilog to create functional RTL that meets power, performance, and area requirements.
• Experience and/or education applying advanced computer architecture knowledge to design CPUs.
• Experience and/or education applying VLSI knowledge to improve CPU frequency, power, and area.
• Experience and/or education employing out-of-order superscalar processor techniques in CPU design.
• Experience and/or education applying advanced branch prediction techniques to improve CPU branch predictors.
• Experience and/or education using cache hierarchy knowledge to improve CPU cache performance.
• Experience and/or education applying modeling skills in C++, Python, and Perl to develop performance and power concepts.
• Experience and/or education applying knowledge of power-performance curves and researching low-power, high-performance architectures and techniques.
• Experience and/or education applying CPU architecture knowledge to develop power models for evaluating next-generation CPU power trade-offs.
• Experience and/or education using knowledge of CPU workloads and characteristics, including code footprint, data footprint, and usage, to evaluate power, performance, and area trade-offs.

Responsibilities

• Perform micro-architecture development and specification, from high-level architectural exploration and research through detailed specification.
• Develop, assess, and refine RTL designs to meet power, performance, area, and timing goals.
• Explore high-performance strategies and work with the performance verification team to verify that RTL meets performance targets.
• Work with multifunctional engineering teams to implement and verify physical design aspects, including timing, area, reliability, testability, and power.
• Implement CPU design modules that meet performance and power goals.
• Use debugging skills and knowledge of C/C++ and Perl to support scripts and feature exploration.
• Support the verification team in testbench development, formal methods, and simulation/emulation for formal verification.
• Work with the Design Verification team on required modifications to ensure designs are functionally correct.
• Explore performance features by developing micro-architectural ideas and working with architects to assess feasibility through RTL changes.
• Identify power-hungry hardware blocks and reduce their power consumption through micro-architectural changes with minimal performance impact.
• Work with the Physical Design team to reduce timing pressure and achieve timing goals and closure.
• Apply CPU architecture, workload, and power-modeling knowledge to evaluate power, performance, and area trade-offs for CPU designs.

Benefits

• Comprehensive medical coverage
• Comprehensive dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple
• Potential discretionary bonuses or commission payments
• Potential relocation
• Opportunity to receive discretionary restricted stock unit awards
• Ability to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan

What This Job Offers

• Job Type: Full-time