FE Engineer

Apple • San Diego, CA

3d • $156,956 - $214,300 • Onsite

About The Position

Apple Inc. is hiring an FE Engineer in San Diego, California. The role involves defining microarchitecture; designing RTL in SystemVerilog/Verilog; integrating and verifying IP; implementing RTL low-power design and running RTL power analysis; ensuring designs are lint-free and CDC-clean; and performing synthesis and timing constraint work. The engineer collaborates with system, algorithm, and firmware teams to support performance and power efficiency. The stated work schedule is 40 hours per week.

The annual base pay range is $156,956–$214,300, with actual base pay depending on skills, qualifications, experience, and location. The posting also describes potential employee stock programs, medical and dental coverage, retirement benefits, discounted products and free services, tuition reimbursement for certain career-related education, and possible discretionary bonuses or commission payments and relocation assistance. Benefits and compensation are subject to applicable eligibility requirements and plan terms.

Requirements

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Communication Engineering, or a related field.
• Three years of experience in the job offered or a related occupation.
• Experience using SystemVerilog or Verilog to write RTL for high-speed communication IPs.
• Experience using scripting languages such as Python, Perl, or TCL, including automating RTL integration and verification, synthesis, and timing analysis.
• Experience with CDC and RDC tools and techniques, and knowledge of multiple clock and reset domains to resolve issues.
• Experience in RTL design with complex FSMs and power-saving features.
• Experience in IP integration, including clock/reset module design, clock-gating implementation, and fabric/bus system configuration and design.
• Knowledge of low-power design concepts and implementation, including clock gating, power gating, and DVFS.
• Knowledge of high-speed interfaces and design, including AXI/AHB buses and peripherals.
• Experience using Synopsys and Cadence synthesis tools and setting constraints, and knowledge of LEC/LEQ.
• Understanding of computer architecture and SoCs.
• Knowledge of and experience with wireless communication.

Responsibilities

• Define microarchitecture.
• Design RTL using SystemVerilog/Verilog.
• Integrate and verify IP.
• Implement RTL low-power design and run RTL power analysis tools.
• Run tools to ensure designs are lint-free and CDC-clean.
• Perform synthesis and establish timing constraints.
• Collaborate with system, algorithm, and firmware teams to support performance and power efficiency.

Benefits

• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and discounted stock purchases through the Employee Stock Purchase Plan, subject to eligibility and plan terms.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• The role might be eligible for discretionary bonuses or commission payments.
• The role might be eligible for relocation assistance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level