FE Engineer
About The Position
Apple Inc. is hiring an FE Engineer in Austin, Texas. The role works across vertical product models and contributes to delivering products to customers. The engineer collaborates with Architecture to understand design performance goals, correlates RTL performance with model performance, performs detailed performance analysis, identifies bottlenecks, and coordinates with Architecture to improve performance. The role defines performance statistics and standard methodologies to support debugging and performance correlation. It works with Architecture, Modeling, Micro-Architecture, Design, and Verification teams to define performance test plans and testing methodologies. Responsibilities also include developing SystemVerilog and C++ testbench infrastructure to monitor, check, and cover on-chip activity; architecting and implementing analysis and visualization methods for simulation performance data; and reviewing performance-validation results with cross-functional audiences. The position requires working independently, leading work aligned with project goals, and supporting multifunctional engineering efforts. Work schedule: 40 hours per week.
Requirements
- Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
- At least 2 years of experience in the job offered or a related position.
- Experience in computer architecture, including cache coherency, cache hierarchy fundamentals, and fabric interconnect fundamentals, to help debug performance bottlenecks.
- Experience with data structures and algorithms, including working with Python, C++, and SystemVerilog in multi-language codebases.
- Experience with object-oriented programming, including working with Python, C++, and SystemVerilog in multi-language codebases.
- Experience using waveform viewers to debug hardware performance bottlenecks, including developing SystemVerilog monitors to automate performance-statistic collection.
- Experience using C and C++, including updating and reviewing software models used to represent hardware.
- Experience scripting in Python and Perl to analyze and visually represent performance data.
- Experience in design verification to help develop robust test plans.
Responsibilities
- Work across vertical product models to support timely delivery of products to customers.
- Work with Architecture to understand design performance goals.
- Correlate RTL performance against model performance.
- Perform in-depth performance analysis of designs and report findings.
- Identify design performance bottlenecks and coordinate with Architecture to improve performance.
- Define performance statistics and standard methodologies to improve debugging and performance correlation.
- Work with Architecture, Modeling, Micro-Architecture, Design, and Verification teams to define performance test plans.
- Drive the definition of testing methodologies for executing test plans.
- Develop SystemVerilog and C++ testbench infrastructure to monitor, check, and cover on-chip activity.
- Architect and implement methods for analyzing and visualizing simulation performance data.
- Review performance-validation results and analysis with cross-functional audiences.
- Work independently, lead work aligned with project goals, and support multifunctional engineering efforts.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
