FE Engineer

Apple•Austin, TX

2d•Onsite

About The Position

Apple Inc. is hiring an FE Engineer in Austin, Texas. The role works across vertical product models and contributes to delivering products to customers. The engineer partners with Architecture to understand design performance goals, correlates RTL performance against model performance, analyzes design performance, identifies bottlenecks, and coordinates with Architecture to improve performance. The role defines performance statistics and methodologies to support debugging and improve performance correlation. The engineer also works with Architecture, Modeling, Micro-Architecture, Design, and Verification teams to define performance test plans and testing methodology. Responsibilities include developing SystemVerilog and C++ testbench infrastructure to monitor, check, and cover on-chip activity; architecting and implementing data-analysis and visualization methods for simulation performance data; and reviewing performance-validation results and analysis with cross-functional teams. The position requires working independently, leading work aligned with project goals, and supporting multifunctional engineering efforts. The stated schedule is 40 hours per week.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
Two years of experience in the job offered or a related position.
Experience in computer architecture, including cache coherency, cache hierarchy fundamentals, and fabric interconnect fundamentals, to debug performance bottlenecks.
Experience with data structures and algorithms, using Python, C++, and SystemVerilog in multi-language codebases.
Experience with object-oriented programming, using Python, C++, and SystemVerilog in multi-language codebases.
Experience using waveform viewers to debug hardware performance bottlenecks, including developing SystemVerilog monitors to automate performance-statistic collection.
Experience using C and C++, including updating and reviewing software models that represent hardware.
Experience scripting in Python and Perl to analyze and visually represent performance data.
Experience in design verification to help develop robust test plans.

Responsibilities

Work across vertical product models to help deliver products to customers quickly.
Work with Architecture to understand design performance goals.
Correlate RTL performance against model performance.
Perform in-depth design performance analysis and report findings.
Identify design performance bottlenecks and coordinate with Architecture to improve performance.
Define performance statistics and standard methodologies for performance debugging and correlation.
Work independently, lead work aligned with project goals, and support multifunctional engineering efforts.
Collaborate with Architecture, Modeling, Micro-Architecture, Design, and Verification teams to define performance test plans.
Drive the testing methodology for executing the test plan.
Develop SystemVerilog and C++ testbench infrastructure to monitor, check, and cover on-chip activity.
Architect and implement data-analysis and visualization methodologies for simulation performance data.
Review performance-validation results and analysis with cross-functional teams.