Principal CAD RTL Methodology and Design Engineer

Ericsson • Austin, TX

16h • Onsite

About The Position

Ericsson is seeking a hands-on technical leader to own RTL design methodology and static signoff flows for ASIC and FPGA programs supporting its 5G and 6G portfolio. The role combines RTL design with methodology leadership, software engineering, and practical AI use to improve design quality, IP reuse, and time to a qualified netlist. Work includes programs at advanced process nodes, including Intel 18A and TSMC 3/2nm. Approximately half of the role is spent on RTL design so that methodology decisions remain grounded in product work.

The engineer will work across RTL design automation, verification methodology, and OneRun, Ericsson’s front-end flow orchestration platform. They will partner with IP and SoC design leads, domain methodology leads, back-end teams, and EDA vendors across Austin, Stockholm, Lund, and India. The position owns technical direction and qualified methodology and partners with the Silicon CAD Technical Program Manager on integrated delivery and adoption. Project design leads retain RTL signoff approval.

The role defines RTL coding standards and signoff criteria; leads lint, CDC, and RDC methodology; delivers vendor-agnostic static signoff automation; advances reusable RTL frameworks and register generation; applies AI tools to RTL engineering with engineering review; and improves front-end-to-back-end handoff checks. Changes are to be introduced through representative pilots without disrupting active tapeout schedules.

Requirements

• At least 10 years of experience in ASIC/SoC RTL design and front-end methodology, with evidence of production deployment and successful tapeout contributions.
• Deep hands-on expertise in SystemVerilog/Verilog RTL design and microarchitecture for complex IP and SoC blocks, including parameterized and low-power design with UPF.
• Strong experience with Synopsys VC SpyGlass and/or Cadence JasperGold for lint, CDC, and RDC.
• Understanding of synthesis, timing, and DFT dependencies.
• Strong Python and scripting skills.
• Experience building maintainable automation using Linux, version control, code review, CI, automated tests, and controlled releases.
• Demonstrated ability to set standards adopted by design teams, explain technical trade-offs, and lead distributed teams through technical credibility.
• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Nice To Haves

• Specialist depth in one or more signoff domains; expertise in every domain is not required.

Responsibilities

• Define and govern RTL coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams; mentor engineers in RTL best practices.
• Architect structural, formal, and hybrid CDC and RDC flows, including progressive goals and hierarchical signoff using abstract models and clock/reset constraints.
• Keep signoff criteria independent of specific tools.
• Deliver single-command static signoff in OneRun using standard project templates and Jenkins CI quality gates.
• Qualify rule mapping between vendor tools on clean and dirty RTL before production use.
• Architect configurable RTL frameworks and standard interfaces to support multi-program IP reuse.
• Set the strategy for the next-generation register generation tool and ensure generated RTL is signoff-clean.
• Use and improve AI tools such as ChipAgents and Kiro for RTL development, documentation, code conversion, and lint and CDC triage; evaluate results against manual baselines and retain engineering review.
• Define RTL quality, SDC, and UPF checks for netlist handoff with synthesis, DFT, and back-end teams.
• Roll out methodology changes through representative pilots without disrupting active tapeout schedules.
• Partner with the Silicon CAD Technical Program Manager on integrated delivery and adoption, and collaborate with design teams and EDA vendors across distributed locations.

Benefits

• Annual short-term variable compensation bonus, subject to eligibility and pro-ration rules.
• Choice of three medical plan options and a dental plan option, with company credits toward premiums for employees and eligible covered dependents.
• 401(k) plan with an automatic 3% company contribution and matching contributions up to 4% when the employee contributes at least 5% of eligible pay.
• Company-paid basic life insurance, basic accidental death and dismemberment coverage, and short-term and long-term disability coverage.
• Option to participate in Ericsson’s Stock Purchase Plan.
• Minimum 15 days of accrued vacation for new employees, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually; paid time off is prorated based on start date.
• Up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
• Financial wellness programs.
• Educational assistance.
• Matching gifts.
• Recognition programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior