Principal PCS/PMA RTL Design Engineer

Astera Labs•San Jose, CA

5d•Onsite

About The Position

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join its San Jose design team. The role focuses on Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards, including Ethernet, PCIe, UCIe, and UALink. The engineer will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs, translating microarchitectural specifications into robust, synthesizable RTL. The position involves close collaboration with architects and teams across SerDes/analog, verification, physical design, DFT, firmware, systems, and validation. The engineer will help deliver designs through synthesis, timing closure, tapeout, and silicon validation, contributing to multi-protocol, multi-lane PHY digital design for next-generation AI and cloud infrastructure.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
3 or more years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.
Hands-on experience developing RTL using Verilog or SystemVerilog.
Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
Working knowledge of at least one high-speed serial protocol at the PCS/PHY layer, such as Ethernet, PCIe, UCIe, UALink, or CXL.
Experience with RTL simulation, debugging, synthesis, and basic timing analysis.
Familiarity with ASIC design flows and collaboration across design and verification teams.
Strong communication skills and ability to work effectively in a collaborative, fast-paced environment.
Ability and willingness to work onsite in San Jose, California.

Nice To Haves

Master's degree.
Direct experience designing PCS, PMA, or PHY digital logic for Ethernet, PCIe, UCIe, UALink, CXL, or similar standards.
Experience with PAM4 signaling, FEC, lane deskew/alignment, link training, and equalization control.
Familiarity with the PIPE specification, IEEE 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.
Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.
Familiarity with interconnect, networking, or data-center ASICs such as retimers, switches, NICs, DPUs, SmartNICs, or NoCs.
Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.
Experience with STA using Synopsys PrimeTime or Cadence Tempus.
Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.
Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.
Experience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation.
Exposure to advanced-node CMOS design, tapeout, silicon bring-up, or post-silicon validation, including BER measurements and lab debug.
Experience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges.

Responsibilities

Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.
Implement PCS functions including line encoding and decoding, scrambling and descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation.
Implement forward error correction functions, FEC framing and interleaving, and associated error counters and status logic.
Implement PMA digital interface logic for SerDes datapaths, CDR control, equalization and link-training control, calibration, and adaptation.
Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation and checking, loopback modes, and BIST features.
Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic.
Design reusable, configurable RTL modules supporting multiple protocols, data rates, and lane configurations.
Integrate internal and third-party IP, including analog/mixed-signal PHY macros, following established design and coding methodologies.
Participate in design reviews and improve RTL quality, reuse, latency, performance, power, and area.
Collaborate with verification engineers on functional requirements, test plans, coverage goals, and protocol compliance.
Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis.
Support lint, CDC, RDC, RTL quality checks, UVM-based verification, functional and integration issue resolution, and gate-level simulation debug as needed.
Support logic synthesis, constraints development, and implementation flows for high-speed, wide-datapath designs.
Perform static timing analysis and help resolve setup, hold, clock, and interface timing issues, including at SerDes and PHY boundaries.
Support timing closure, power optimization, PPA trade-offs, DFT integration, scan requirements, low-power intent, ECOs, and implementation signoff.
Review reports and debug issues from Cadence and/or Synopsys digital design flows.
Support block-level and subsystem-level integration through tapeout milestones.
Collaborate with SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams.
Participate in silicon bring-up, link bring-up, interoperability and compliance testing, post-silicon debug, and failure analysis as opportunities arise.
Document design decisions, issues, and technical solutions for cross-functional stakeholders.