RTL Design Engineer

Rivian•Palo Alto, CA

16h•Onsite

About The Position

Rivian is seeking an RTL Design Engineer to join its Neural Network Engine (NNE) design team in Palo Alto. The role involves defining microarchitecture and delivering production-quality RTL for compute, memory, datapath, and control blocks in an advanced SoC environment. The engineer will translate architectural and physical-design requirements into microarchitecture specifications and partner with design verification, physical design, firmware, compiler, and silicon-validation teams. The position calls for ownership of a block from definition through implementation, debug, quality checks, and integration.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
Professional experience designing and delivering synthesizable RTL for ASIC, SoC, or other complex digital hardware.
Strong proficiency in Verilog and SystemVerilog.
Understanding of synchronous digital design, pipelining, finite-state machines, interfaces, memories, and reset/clock behavior.
Experience debugging RTL through simulation and waveform analysis.
Ability to read and contribute to architectural, microarchitectural, interface, and verification specifications.
Strong written and verbal communication skills, including the ability to write clear design documentation, with a collaborative and ownership-oriented approach.
A disciplined approach to writing simple, readable specifications that enable development of clean, reusable, and verifiable RTL.
Curiosity about how architecture, implementation, verification, and physical design interact.
Comfort working through ambiguous problems, making explicit assumptions, and iterating with partner teams.
A bias toward early validation, clear documentation, and high-quality handoffs.
Ability to balance block-level ownership with system-level thinking.

Nice To Haves

Experience with compute engines, neural-network accelerators, floating point computation, memory subsystems, high-throughput datapaths, or SoC control logic.
Experience with clock-domain crossings, reset-domain crossings, clock gating, power-aware design, or functional-safety concepts.
Familiarity with RTL quality and implementation flows such as lint, CDC/RDC, formal/equivalence checking, synthesis, static timing analysis, and power analysis.
Experience with Synopsys VCS, Verdi, or comparable simulation and debug tools.
Experience building Python or other software models to explore architecture, validate behavior, or accelerate RTL development.
Experience with Git-based development, code review, continuous integration, and automated regressions.
Familiarity with physical-design constraints and PPA trade-offs.
Experience working across hardware, firmware, compiler, verification, physical design, and silicon-validation teams.
Experience developing hardware for automotive, safety-critical, or other reliability-sensitive applications.

Responsibilities

Translate architectural requirements into clear microarchitectural specifications and design documentation.
Analyze performance and power characteristics of existing hardware and software to identify areas for improvement.
Develop and utilize AI agents to streamline RTL development tasks.
Define and review block-level interfaces, including data movement, handshakes, clocking, reset behavior, and error handling.
Design, implement, integrate, and debug synthesizable RTL for NNE blocks and interfaces.
Design with performance, power, area, functional safety, and physical implementation constraints in mind.
Collaborate with design verification engineers to create test plans, assertions, coverage goals, and debug strategies.
Use simulation, lint, CDC/RDC, formal or equivalence checking, synthesis, and timing analysis to evaluate and improve RTL quality.
Investigate functional, performance, timing, and power issues across RTL, verification, and implementation flows.
Participate in design reviews and contribute to coding standards, reusable RTL patterns, and development methodology improvements.
Support block integration, regression closure, RTL handoff, and pre-silicon validation.
Communicate design decisions, assumptions, risks, and trade-offs clearly across partner teams.

Benefits

Paid vacation
Paid sick leave
Life insurance
Medical insurance
Dental insurance
Vision insurance
Short-term disability insurance
Long-term disability insurance
Opportunity to participate in Rivian’s 401(k) Plan, subject to eligibility requirements
Opportunity to participate in Rivian’s Employee Stock Purchase Program, subject to eligibility requirements