RTL Design Engineer, TPU

Google•Sunnyvale, CA

4d•$163,000 - $236,000

About The Position

Join Google's team developing SoC-level Register-Transfer Level (RTL) design for data center accelerators. The role focuses on designing RTL intellectual property for management and control subsystems and developing SoC infrastructure and methodology, including clocking, reset, error handling, debug, chip management, and SoC chassis. You will help shape TPU technology used in AI/ML applications and contribute design and verification expertise focused on TPU architecture and integration in AI/ML-driven systems. The role involves building a broad understanding of accelerator development from concept through production. It is highly cross-functional, requiring coordination and co-design with software and system hardware counterparts, as well as leadership of efforts involving multiple stakeholders.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience with scripting languages.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
8 years of experience in ASIC design.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience with chip management, clocking, reset, and peripherals such as I2C, SPI, and UART.
Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

Create and review management and control subsystem design microarchitecture specifications.
Develop SystemVerilog RTL implementing logic for ASIC products in accordance with established coding and quality guidelines.
Work with architecture and power teams to evaluate features and their impact.
Work with design validation teams to create test plans, verify designs, and debug design RTL.
Work with physical design teams to ensure the design meets physical requirements and achieves timing closure.