RTL Design Engineer

Advanced Micro Devices, Inc • Austin, TX

2d • Onsite

About The Position

AMD is seeking a highly motivated RTL IP Design Engineer to join its Security IP (SECIP) Design team. The team develops and verifies embedded microprocessor subsystems and hardware accelerators for AMD System-on-Chip products across client, server, graphics, and gaming platforms. These designs support areas such as security policy management, cryptography, data compression, high-throughput DMA, and power management.

The engineer will contribute to block-level RTL design and subsystem-level integration, working with the IP Architecture team to define functional specifications, establish and track design objectives, and develop and optimize RTL. The role involves delivering scalable, high-quality designs that meet performance, power, and area targets, while collaborating with design, verification, implementation, integration, emulation, and post-silicon validation teams. The position is based in Austin, Texas, with Markham, Ontario also considered. It is not eligible for visa sponsorship.

Requirements

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Strong understanding of CPU and embedded microprocessor subsystem architectures and datapath-oriented accelerator microarchitectures.
• Proficiency in Verilog and SystemVerilog.
• Knowledge of scripting languages such as Python, Tcl, Perl, Ruby, and Make.
• Knowledge of traditional and AI-powered RTL design and verification methodologies, industry best practices, and C-DPI-based verification techniques.
• Strong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA.
• Experience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification.

Nice To Haves

• Master's degree.
• Experience with FPGA-based emulation and prototyping methodologies.
• Domain-specific expertise in security, processor subsystems, accelerators, or related areas.
• Demonstrated technical leadership capabilities for senior-level candidates.

Responsibilities

• Develop and maintain block-level RTL IP and microprocessor subsystem specifications, microarchitecture, RTL implementations, design methodologies, and infrastructure.
• Design, implement, and debug RTL using AI-powered methodologies, directed C-DPI-based testing, and verification team testbenches and regression environments to achieve functional and coverage closure.
• Analyze regression failures, debug simulations, evaluate coverage, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.
• Contribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification best practices.
• Debug and resolve subsystem and SoC integration issues with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams.
• Provide technical leadership in IP architecture, RTL design methodologies, and critical problem resolution, commensurate with experience level.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level